AN1139 STMicroelectronics, AN1139 Datasheet - Page 24

• Manufacturer Part Number: AN1139
• Description: L6254 - L6268 - L6269 12V DISK DRIVE POWER COMBO IC
• Manufacturer: STMicroelectronics

AN1139 APPLICATION NOTE
commutation timings. The complete control loop is on chip and the speed is controlled by a reference clock at
pin SYS_CLK (pin#15).
The speed control loop uses a frequency locked loop (FLL) which in conjunction with an external compensation
network brings the frequency of the tachometer signal to be equal to the internally generated reference frequen-
cy. The tachometer signal can either be the BEMF signal divided down to a once per mechanical or electrical
revolution signal or an externally generated tachometer signal, sector burst. The output of the speed control is
a current demand signal that goes to the Spindle Driver.
There are a "Fine" and a "Coarse" counters that define the speed of the motor. The register #4 and half of the
#5 are the FLL Coarse Counter registers (12bits total, only count down to zero). The register #6 and the other
half of the #5 are the FLL Fine Counter registers (11bits, count down to 2’s complement of the 11 bit value). The
figure #9 shows the counters.
Figure 9. FLL Counters
In more detail, those three registers are used in conjunction with two down counters which form a frequency
detector that in turn creates feedback through to a charge pump to maintain the motor’s speed regulation. The
frequency clock applied to SYS_CLK pin is internally divided by a factor of 5.
The coarse counter is 12 bits and it is clocked at 1/64th the rate of the internal frequency clock. The fine counter
is 11 bits and it is clocked at 1/4th the rate of the internal frequency clock. The on-chip Frequency Locked Loop
uses the electrical or mechanical cycle pulses, according to the Reg#2.5 setting to adjust the speed of the
motor. Upon the first pulse, the coarse register's contents (loaded via the serial port) is loaded into the internal
coarse counter which immediately starts to count down. When this coarse counter reaches zero, the fine
counter is then loaded from its corresponding register. The fine counter then also immediately starts to count
down. The fine counter can count down through zero and continue counting down to the 2's complement of the
original fine counter value.
The period between the start of the coarse counter and the zero crossing during the fine counter operation is
24/64
"Previous" zero
register v alue
register v alue
cro ssing
FLL Course
F LL F ine
C ourse c ounter
c ounting down
between z ero crossings
Desired period
Fine c ounter
countin g down
Z ero crossing
expec ted here
e.g. Actual
cro ssing
zero
and actual z ero c ros sing. T his value is fed into
A ctual error betwee n ex pected z ero crossing
the charge pum p to either speed up or slow
down the rotation.
Course counter
counting down
e.g. Actual
crossing
zero
F ine coun ter
c ounting down
Time