AN1356 STMicroelectronics, AN1356 Datasheet - Page 24

• Manufacturer Part Number: AN1356
• Description: PSDSOFT EXPRESS AND PSD4235G2 DESIGN GUIDE
• Manufacturer: STMicroelectronics

AN1356 - APPLICATION NOTE
SECOND DESIGN EXAMPLE – ISP, FULL IAP & CPLD LOGIC ELEMENTS
This second design example builds upon the first by adding true IAP capability. You will see how to
execute from secondary PSD Flash memory in program space while programming the main PSD Flash
memory in data space, then move main PSD Flash memory to program space for execution. We will also
create some complex logic in the CPLD requiring use of the Extended Design Assistant.
Memory Map
Figure 27 and Figure 28 represent the system memory maps for this design.
Figure 27 represents the system memory map at power-up and after reset. This map is also valid during
IAP. Notice that all of the main PSD Flash memory is initially in Data space so that the P51XA can write
to it during IAP. Also notice that all of the secondary PSD Flash memory is initially in Program space so
the P51XA can execute code from it during IAP. The choice for this initial placement of memory in Program
or Data space was made within PSDsoft Express (‘Define MCU and PSD’ in flow diagram).
Figure 28 represents the system memory map after IAP is complete. All of main PSD Flash memory has
moved to Program space. The PSD has a control register (named the VM register) that allows the P51XA
to change the definition of Program space and Data space at run-time for IAP purposes. This VM register
is accessed at an address offset from the base address, “csiop”.
Sequence of events for IAP:
To accomplish this IAP function, no chip-select equations have to change from the first simple design
example. Only the VM register must be accessed at run time as described above.
For MCUs/MPUs without Harvard architecture (Harvard: separate program and data address spaces) the
VM register is not needed since there is only one address space for both code and data. IAP is much
simpler for these MCUs/MPUs.
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Figure 27 - at power on or after reset, the P51XA boots from secondary PSD Flash memory
Figure 27 – P51XA runs a checksum of the main PSD Flash memory in Data space
Figure 27 - If needed, P51XA programs and verifies main PSD Flash memory in Data space via the
UART
Figure 27 – P51XA writes 06h to the VM register to place main PSD Flash memory into Program space
Figure 28 – main Flash memory has moved to program space as a result of writing 06h to VM register
Figure 28 – P51XA can now execute application code from either main or secondary PSD Flash
memory