AN1356 STMicroelectronics, AN1356 Datasheet - Page 3

• Manufacturer Part Number: AN1356
• Description: PSDSOFT EXPRESS AND PSD4235G2 DESIGN GUIDE
• Manufacturer: STMicroelectronics

Figure 2. Embedded Flash memory system capable of ISP and IAP (2 devices)
By design, the IAP method described above requires MCU participation to exercise a communication
channel to implement a download to the main Flash memory. The PSD4235G2 also offers an alternative
method (ISP) to program the PSD using a built-in IEEE-1149 JTAG interface requiring no MCU
participation. This means that a completely blank PSD can be soldered into place and the entire chip can
be programmed in-system in just a few seconds using ST’s FlashLINK™ JTAG cable and PSDsoft
development software. No P51XA firmware needs to be written, just plug in the FlashLINK™ cable to your
PC parallel port and begin programming memory, logic, and configuration. This is a powerful feature of
the PSD4235G2 that allows immediate development of application code in your lab, smart manufacturing
techniques, and easy field updates.
PSDsoft Express is available from our website. The availability of the FlashLINK™ cable is also detailed
there.
Let’s take a quick look inside the EasyFLASH™ PSD4235G2, as shown in Figure 3. You can see the three
independent memory arrays, which are selected on a segment basis when the proper MCU address is
decoded in the Decode PLD. The page register participates in memory decoding, which greatly simplifies
paging. The MCU address, data, and control signals are routed throughout the chip and can be used within
the Complex PLD (CPLD). The CPLD has 16 Output Microcells (OMCs), each containing a flip-flop and
combinatorial logic. The CPLD also has 24 Input MicroCells (IMCs) used for conditioning incoming
signals. The MCU has direct memory-mapped access to both OMCs and IMCs. Additionally, the CPLD
contains 8 programmable external chip-select outputs. There are 52 I/O pins that can be individually
configured for many different functions. A power management scheme can selectively shut down parts of
the chip and tailor special power saving mechanisms on-the-fly. The security feature can block access to
all areas of the chip from a device programmer/reader. Finally, the self-contained JTAG-ISP controller
allows programming of all areas of the chip.
In the second design example of this document, you will see how to use the CPLD to implement a loadable
counter, a state machine, combinatorial logic, and other functions using OMCs, IMCs, the page register,
and external chip-selects.
Computer
Host
Communication
Channel
Embedded System
MPU/MCU
16-bit
512 KByte Flash
32 KByte Flash
8KByte SRAM
Programmable Logic
I/O
PSD4x35G2
AN1356 - APPLICATION NOTE
System
I/O
JTAG
ISP
AI04060
3/49