AN1356 STMicroelectronics, AN1356 Datasheet - Page 40

• Manufacturer Part Number: AN1356
• Description: PSDSOFT EXPRESS AND PSD4235G2 DESIGN GUIDE
• Manufacturer: STMicroelectronics

AN1356 - APPLICATION NOTE
THIRD DESIGN EXAMPLE – ISP AND ADVANCED IAP
The third design example adds enhanced IAP features. The physical connections between the MCU and
PSD4235G2 do not change, but chip-selects (memory map) and PSD page register definitions do change.
We will not change any of the CPLD logic in this design.
This enhanced design derives the most utility out of the PSD architecture by providing a means to replace
the secondary PSD Flash memory with a segment of main PSDflash memory (swapping) after IAP is
complete. These benefits result:
Memory Map
The memory map for this design is a sequence of four steps shown in Figure 45 through to Figure 48.
Figure 45 is the memory map at system power-on or system reset. The swap bit and unlock bit are defined
as two of the eight PSD page register bits. Here’s the sequence after power-up or reset:
Figure 48 shows the final memory map. The P51XA now has a full 512 KBytes of main Flash memory (fs0
.. fs7) in Program space, 16 KBytes secondary Flash memory (csboot2/csboot3) in Data space for general
data storage, as well as 8 KBytes of battery backed SRAM (rs0) in Data space. The 16 KBytes of IAP
loader code (csboot0/csboot1) is no longer in MCU “executable” position.
If the P51XA needs to update the IAP loader code that resides in secondary Flash memory segments
csboot0 and csboot1, it may do so only after setting the unlock bit in the page register. Note that all page
register bits are cleared to zero at power-on and at any system reset.
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IAP bootloader code in secondary PSD Flash memory can be updated in the field while executing from
main PSD Flash memory.
The entire application can be executed from main Flash memory after IAP is complete.
The system software designer can make use of two sets of MCU interrupt vectors/routines and low-level
code: one set during IAP (contained in secondary Flash memory) and a different set after IAP
(contained in main Flash memory).
The secondary PSD Flash memory can be split in half. One half used for boot loader code during IAP
and the other half used as general data storage after IAP.
Figure 45: P51XA boots from secondary Flash memory (csboot0/csboot1) at address 0000, the VM
register contains the initial value of 12h from the point-and-click settings in PSDsoft.
Figure 45: P51XA performs a checksum of main Flash memory (fs0..fs7) in Data space
Figure 45: P51XA downloads to main Flash memory from host computer if needed and validate
contents
Figure 45: P51XA writes 06h to PSD VM register
Figure 46: Main Flash memory has moved to Program space because of 06h in VM register
Figure 46: P51XA sets swap bit to logic one (writes to PSD page register)
Figure 47: Secondary Flash memory (csboot0/sboot1) has moved out of the MCU address range 0000
to 3FFF and main Flash memory (fs0) has moved into its place because of the swap bit. This swapping
action is implemented by qualifying the chip-selects with the swap signal. Also as a result of setting the
swap bit, the secondary Flash memory segments csboot2 and csboot3 appear. They cannot be used
for data until after the next step.
Figure 47: P51XA writes 0Ch to PSD VM register.
Figure 48: Secondary Flash memory (csboot0..csboot3) has moved to Data space because of 0Ch in
VM register. Now secondary Flash memory segments csboot2 and csboot3 can be used for general
data.