AN1356 STMicroelectronics, AN1356 Datasheet - Page 6

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AN1356

Manufacturer Part Number
AN1356
Description
PSDSOFT EXPRESS AND PSD4235G2 DESIGN GUIDE
Manufacturer
STMicroelectronics
Datasheet
AN1356 - APPLICATION NOTE
FIRST DESIGN EXAMPLE - ISP CAPABLE SYSTEM, LIMITED IAP
The first design example is capable of ISP and limited IAP. It outlines the steps required to get a Flash
memory P51XA system up and running quickly. The 32 KBytes of PSD secondary Flash memory will be
programmed with P51XA firmware (over the JTAG-ISP channel) that will execute low-level system
hardware tests. This firmware is also able to access 512 KBytes of main PSD Flash memory, used as data
only — not program space. This provides a way to develop code to erase and write to main PSD Flash
memory while executing from secondary Flash memory. The second and third design examples take full
advantage of concurrent memory operation and IAP, by allowing program execution from main Flash
memory in addition to writing to it. You should become familiar with this first design before using the
second and third.
Memory Map
For this first simple design, a PSD4235G2 is used with the following memories:
Note: PSD memory segment address locations are defined using PSDsoft Express ™.
We’ll use the PSD’s secondary Flash memory to hold the boot code, P51XA interrupt vectors, hardware
drivers, and common functions including routines that erase/program main PSD Flash memory. For this
example, we’ll execute from the PSD’s secondary Flash memory only and use the PSD’s main Flash
memory as data. See the memory map in Figure 5.
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512 Kbytes main Flash memory, broken into eight 64 Kbyte segments denoted fs
32 Kbytes secondary Flash memory, broken into four 8 Kbyte segments denoted csboot
8 Kbyte SRAM denoted rs0
256-byte PSD4235 control registers denoted csiop.
i (i = 0-7)
j (j = 0-3)
.

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