AN2329 Freescale Semiconductor / Motorola, AN2329 Datasheet - Page 14

• Manufacturer Part Number: AN2329
• Description: Interfacing the MSC8101 to SDRAM on the MSC8101ADS
• Manufacturer: Freescale Semiconductor / Motorola

Programming the MSC8101 SDRAM Machine
3.3.2 Bank-Based Interleaving
14
A0
—
—
A7
A8
A9
Note:
Bank-based interleaving uses the most significant address bits as the bank select for the SDRAM, thus
allowing interleaving only on bank boundaries. It is activated by clearing PSDMR[PBI]. See Table 14
through Table 19.
A10
MSB of start address
MSB of start address
System bus
System bus
Signals
Signals
A11
Driven
partition
partition
Driven
A[0–8]
A[0–7]
Partitioning is affected if a different SDRAM is used. Usually the number of row and column
address lines varies according to the size of the SDRAM. As long as the SDRAM device address
port and the system bus address bus is partitioned according to the correct number of row and
columns address lines, BR, OR, and PSDMR are programmed correctly.
A12
Figure 9. MSC8101 SDRAM Address Multiplexing.
Freescale Semiconductor, Inc.
Table 16. SDRAM Address Port During ACTIVATE for 64-Bit Port Size
Table 17. SDRAM Address Port During ACTIVATE for 32-Bit Port Size
A13
For More Information On This Product,
Table 15. System Bus Address Bus Partition for 32-Bit Port Size
Table 14. System Bus Address Bus Partition for 64-Bit Port Size
A14
A[0–15]
Row
A[0–16]
A15
—
A16
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Internal bank address
Internal bank address
A17
A[9–10]
A[8–9]
A18
(Internal bank select)
(Internal bank select)
/AP
A10
A19
A9
A[16–17]
A[17–18]
A[9-10]
A[8-9]
A20
BNKSEL
A10
A9
A21
A11
A8
A22
A7
A12
A22
A23
A23
A13
A6
A[10–20]
A[11–21]
Row
Row
A14
A24
A24
A5
Column
A25
A25
A15
A4
(Row address)
(Row address)
A26
A16
A26
A3
A[18–28]
A[19–29]
A[10-20]
A[11-21]
A27
A27
A17
A2
A[22–29]
A[21–28]
Column
Column
A28
A28
A1
A18
A29
A29
A0
A19
A30 A31
Column
Row
SDRAM Address
Lines
LSB
A[29–31]
A[30–31]
A[29–31]
A[30–31]
System Bus
LSB
LSB
—
Address