AN2329 Freescale Semiconductor / Motorola, AN2329 Datasheet - Page 18

• Manufacturer Part Number: AN2329
• Description: Interfacing the MSC8101 to SDRAM on the MSC8101ADS
• Manufacturer: Freescale Semiconductor / Motorola

Programming the MSC8101 SDRAM Machine
18
ROWST
PMSEL
17–18
19–22
23–25
28–31
Name
NUMR
BPD
IBID
26
27
—
Reset
0
0
0
0
0
0
Banks Per Device
Sets the number of internal banks per SDRAM device. Note
that for 128-MB SDRAMs, BPD must have a value of 00 or
01.
Row Start Address Bit
Sets the demultiplexed row start address bit. The value of
ROWST depends on PSDMR[PBI].
Number of Row Address Lines
Sets the number of row address lines in the SDRAM device.
Page Mode Select
Selects page mode for the SDRAM connected to the
memory controller bank.
Internal Bank Interleaving Within Same Device Disable
Setting this bit disables bank interleaving between internal
banks of a SDRAM device connected to the chip-select line.
IBID should be set in multi-master bus mode if the SDRAM
device is not connected to the
Reserved. Write to zero for future compatibility.
Freescale Semiconductor, Inc.
Table 21. ORx Bit Settings (SDRAM Mode)
For More Information On This Product,
Description
BNKSEL
Go to: www.freescale.com
SDRAM Page Information
pins.
00
01
10
11
For PSDMR[PBI] = 0
0010 A7.
0100 A8.
0110 A9.
1000 A10.
1010 A11.
1100 A12.
1110 A13.
Other values are reserved.
For PSDMR[PBI] = 1
0000 A0.
0001
0010
...
1000 A8 (for 64-bit port size).
1001
1101–1111 Reserved.
000
001
010
011
100
101
110
111
0
1
0
1
2 internal banks per device.
4 internal banks per device (settings are common
for both 32-bit and 64-bit port sizes).
8 internal banks per device (not valid for 128-MB
SDRAMs).
Reserved.
9 row address lines.
10 row address lines.
11 row address lines (settings are common for
both 32-bit and 64-bit port sizes).
12 row address lines.
13 row address lines.
14 row address lines.
15 row address lines.
16 row address lines.
Back-to-back page mode (normal operation). Page is
closed when the bus becomes idle.
Page is kept open until a page miss or refresh
occurs.
Enables bank interleaving (setting is common for
both 32-bit and 64-bit port sizes).
Disables bank interleaving.
A1.
A2.
A9 (for 32-bit port size).
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Settings