AN2329 Freescale Semiconductor / Motorola, AN2329 Datasheet - Page 4

• Manufacturer Part Number: AN2329
• Description: Interfacing the MSC8101 to SDRAM on the MSC8101ADS
• Manufacturer: Freescale Semiconductor / Motorola

MT48LC2M32B2TG SDRAM Device
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4
MT48LC2M32B2TG SDRAM Device
The MT48LC2M32B2TG
Figure 3). This register configures basic SDRAM device operation, such as the following:
•
• Burst length (4 beats for 64-bit and 16-bit port sizes, 8 beats for 32-bit and 8-bit port sizes)
• Burst type (sequential or interleaved)
The burst operation uses an on-chip burst counter that increments the column addresses, yielding very
fast burst accesses.
Program to 0 to ensure compatibility
with future devices.
0 program burst length
1 single location access
When the Mode Register Set (
PSDMR[2–4]:OP field must contain a value of 011 to initialize the SDRAM (see Table 22 for details). To
program the SDRAM device for a
32-bit port size, the bits in the MSC8101 PSDMR register must be configured as follows:
• PSDMR[23]:BL = 1
• PSDMR[30–31]:CL = 010
CAS
Refresh and Refresh
A10/Auto Precharge
Pipelined Operation
latency (1, 2, or 3)
Component
CAS Latency
A10
Latency mode. Can be 1 (0b001), 2 (0b010), or 3 (0b011)
*
Counter
Freescale Semiconductor, Inc.
For More Information On This Product,
WB
A9
Figure 3. Mode Register Definition
Standard operation is 00
SDRAM device contains a mode register that is initialized at power-up (see
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A8
Op Mode
Table 1. SDRAM Architecture (Continued)
Operation mode
The MT48LC2M32B2TG SDRAM device employs a three-stage pipeline that allows
new memory accesses to be initiated before the preceding access completes. When
the pipeline is full, data can be accessed on every clock cycle. Along with burst
mode access, this feature significantly improves data transfer performance.
During ACTIVE operation, A[0–10] provide row address information. During read
and write operations, A10 pulled high enables the auto precharge feature, and A10
pulled low disables it. BA[0–1] determine which bank is being read from or written to.
During the refresh operation the SDRAM auto refreshes if Clock Enable (CKE) is
high; it self refreshes if CKE is low. A refresh counter controls row addressing and
tracks the next row number to be refreshed in preparation for the next refresh
command. When the MSC8101ADS board is configured for a 32-bit bus mode, one
SDRAM CKE signal is tied low. When the CKE signal is tied low, the SDRAM device
can retain its values while it is in self refresh mode.
The MSC8101 SDRAM machine accesses a row of the memory matrix by putting an
address on the memory address pins and activating the RAS signal. After a defined
number of clock cycles (known as RAS-to-CAS delay), the column address is put on
the address pins, and the CAS signal is activated to access the correct column of
the memory matrix. Finally, after another defined number of clock cycles (CAS
latency), the data appears on the pins of the RAM.
MRS
A7
CAS
) command is issued during SDRAM initialization, the MSC8101
latency of 2- and 8-beat bursts in Single-Master Bus mode with a
A6
A5
CL
A4
Description
A3
BT
0 Sequential (always 0), 1 interleaved
Burst Length:
4 (0b010) for 16- and 64-bit port sizes
8 (0b011) for 8- and 32-bit port sizes
A2
A1
BL
A0