AN2329 Freescale Semiconductor / Motorola, AN2329 Datasheet - Page 6

• Manufacturer Part Number: AN2329
• Description: Interfacing the MSC8101 to SDRAM on the MSC8101ADS
• Manufacturer: Freescale Semiconductor / Motorola

MT48LC2M32B2TG SDRAM Device
2.2 SDRAM Operations
2.3 SDRAM Row and Column Addressing
6
Table 2 shows the functions of the SDRAM device and the pins associated with them.
Following are important points about these commands to keep in mind:
•
• During load mode register operation,
• During active operation,
• During read and write operation,
• During precharge operation, A10 LOW:
• During a refresh operation, auto refreshes occur if
• During refresh operation, an internal refresh counter controls row addressing; all inputs and I/Os are
• During write inhibit/output high Z operations, the
SDRAM is usually based on a 2-, 4-, or 8-bank architecture. The Micron MT48LC2M32B2TG consists
of 4 banks.
PRECHARGE
(BCR). When BCR[EAV] is cleared, bank select signals are driven on system bus address lines. There is
Command Inhibit (NOP)
No Operation (NOP)
Active
(Select bank and activate Row)
READ (Select bank and column,
and start READ burst)
WRITE (Select bank and column,
and start WRITE burst)
Burst terminate
PRECHARGE (Deactivate row in
bank or banks)
AUTO REFRESH or SELF
REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
CKE
auto precharge feature, and
written.
HIGH: All banks are precharged, and
held low.
“Don't care” except for
writes (zero-clock delay) and reads (two-clock delay).
DQ[8–15]
is high for all SDRAM commands except
Command
BA[0–1]
;
command is applied. Bank select lines are controlled using the Bus Configuration Register
Freescale Semiconductor, Inc.
DQM2
For More Information On This Product,
controls
are bank address inputs that define the bank to which the
Go to: www.freescale.com
CKE
A[0–10]
DQ[16–23]
A10
.
sampled low disables it.
CS
provide the row address, and
A[0–7]
Table 2. SDRAM Truth Table
H
L
L
L
L
L
L
L
L
A[0–10]
; and
BA0
provide the column address.
RAS
BA0
H
H
H
X
H
H
L
L
L
and
DQM3
and
define the opcode written to the SDRAM Mode Register.
BA1
SELF REFRESH
BA1
DQ
controls
CAS
CKE
are “Don't care.”
X
H
H
L
L
L
L
L
L
signals s are activated or deactivated during
determine which bank is precharged.
DQM0
is held high, and self refreshes occur if
BA[0–1]
DQ[24–31]
WE
.
controls
X
H
H
H
H
L
L
L
L
BA[0–1]
determine which bank is read or
A10
Bank/Row
.
Bank/Col
Bank/Col
DQ[0–7]
ADDR
determine which bank is active.
Code
X
X
X
X
X
sampled high enables the
ACTIVE
;
DQM1
OPCODE
,
DQM
READ
Code
H/L
H
X
X
X
X
X
X
L
controls
,
WRITE
A10
ACTIVE
ACTIVE
High Z
DQs
CKE
Valid
X
X
X
X
X
X
X
, or
is