AN2329 Freescale Semiconductor / Motorola, AN2329 Datasheet - Page 7

• Manufacturer Part Number: AN2329
• Description: Interfacing the MSC8101 to SDRAM on the MSC8101ADS
• Manufacturer: Freescale Semiconductor / Motorola

2.4 SDRAM Timing Diagrams
ADDRESS
BA0, BA1
CLKOUT
PSDVAL
SDA10
Data
RAS
CAS
WE
CS
TA
no full address visibility. When BCR[EAV] is set, bank select signals are not driven on the address bus.
Bank select lines are used to drive the
the
environments.
The row address lines are used to activate a specific bank for commands such as
PRECHARGE
bank. The column address lines are used to issue a
WE
applied instead. MT48LC2M32B2TG uses address inputs
during a read or write operation to a specific area in memory when a
This section covers the timing diagrams of the MSC8101’s SDRAM machine interface to SDRAM
during read, write, read burst and write burst operations.
BA[0–1]
signal. If
Freescale Semiconductor, Inc.
. MT48LC2M32B2TG uses address inputs
signals.
For More Information On This Product,
WE
t34
t34
t34
t32a
t32a
RAS-to-CAS
is high, a read operation is applied on the bank, and if
Figure 5. Single Read Transaction
BNKSEL
Row
tAS
tAS
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signals can be used to drive bank select signals in single or multi-master
tAH
tAH
t34
t34
t34
t32a
t32a
BA[0–1]
tAS
Col
signals. You can use the address lines or
tAH
READ
t34
t34
t34
t34
t32a
A[0–10]
tRC
or
A[0–7]
WRITE
CAS Latency
CAS Latency
as row address lines to activate a specific
MT48LC2M32B2TG SDRAM Device
as column address lines to fetch data
command based on the status of the
tLZ
READ
tAC2
WE
/
WRITE
is low, a write operation is
t12a
t11
t11
READ
command executes.
D1
,
BNKSEL
tOH
WRITE
t10
t10
t10
tHZ2
, or
to drive
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