FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 28
FDC37B77X
Manufacturer Part Number
FDC37B77X
Description
ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
Manufacturer
SMSC Corporation
Datasheet
1.FDC37B77X.pdf
(196 pages)
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CONFIGURATION
(CCR)
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy
controller.
values.
PS/2 Model 30 Mode
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy
controller.
values.
BIT 2 NO PRECOMPENSATION
This bit can be set by software, but it has no
functionality. It can be read by bit 2 of the DSR
when in Model 30 register mode. Unaffected by
software reset.
RESET
COND.
RESET
COND.
See Table 11 for the appropriate
See Table 11 for the appropriate
CONTROL
N/A
N/A
7
7
N/A
N/A
6
6
REGISTER
N/A
N/A
5
5
N/A
28
N/A
4
4
BIT 2 - 7 RESERVED
Should be set to a logical "0"
BIT 3 - 7 RESERVED
Should be set to a logical "0"
Table 12 shows the state of the DENSEL pin.
The DENSEL pin is set high after a hardware
reset and is unaffected by the DOR and the
DSR resets.
N/A
N/A
3
3
NOPREC DRATE
N/A
N/A
2
2
DRATE
SEL1
SEL1
1
1
1
1
DRATE
DRATE
SEL0
SEL0
0
0
0
0
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