FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 32

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

SMSC FDC37C672
Model 30 Mode
BITS 0 - 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 6.10 for the settings corresponding to
the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250
Kbps after a hardware reset.
BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in the CCR register.
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
BITS 4 - 6 UNDEFINED
Always read as a logic "0"
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Configuration Register LD8:CRC1[1:0]).
RESET
COND.
CHG
DSK
N/A
7
6
0
0
DATASHEET
5
0
0
Page 32
4
0
0
DMAEN NOPREC DRATE
3
0
2
0
Enhanced Super I/O Controller with Fast IR
SEL1
1
1
DRATE
SEL0
0
0
Rev. 10-29-03
Datasheet