MD1822DB3 Supertex, Inc., MD1822DB3 Datasheet - Page 8
Manufacturer Part Number
JTAG or Boundary Scan mode is an industry standard (IEEE
1149.1, or 1532) serial programming mode. External logic
from a cable, microprocessor, or other device is used to
drive the JTAG speciﬁc pins, Test Data Out (TDO), Test Data
JTAG or Boundary Scan Mode
an adequate “product liability indemnification insurance agreement.”
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the
Input to output delay and fall time of output at V
= 330pF(105V/10.5ns) = 3.2A.
does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
All rights reserved. Unauthorized use or reproduction is prohibited.
Test Mode Select of CPLD.
Test Data In of CPLD.
Test Data Out of CPLD.
Test Clock of CPLD.
Logic Power Supply Ground 0V for programming and testing only.
Logic Power Supply +3.3V for CPLD programming or testing only.
= 10V, V
In (TDI), Test Mode Select (TMS), and Test Clock (TCK).
This mode has gained popularity due to its standardization
and ability to program CPLD through the same four JTAG
pins. The data in this mode is loaded at one bit per TCK.
does not assume responsibility for use of devices described, and limits its liability
/VNN = ±70V, Load = 330pF//2.5k,
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