AD8109 Analog Devices, AD8109 Datasheet

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AD8109

Manufacturer Part Number
AD8109
Description
325 MHz, 8 3 8 Buffered Video Crosspoint Switches
Manufacturer
Analog Devices
Datasheet

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a
PRODUCT DESCRIPTION
The AD8108 and AD8109 are high speed 8 8 video cross-
point switch matrices. They offer a –3 dB signal bandwidth
greater than 250 MHz and channel switch times of less than
25 ns with 1% settling. With –83 dB of crosstalk and –98 dB
isolation (@ 5 MHz), the AD8108/AD8109 are useful in many
high speed applications. The differential gain and differential
*Patent Pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
8
Serial or Parallel Programming of Switch Array
Serial Data Out Allows “Daisy Chaining” of Multiple
Output Disable Allows Connection of Multiple Devices
Pin Compatible with AD8110/AD8111 16
For 16
Complete Solution
Excellent Video Performance
Excellent AC Performance
Low Power of 45 mA
Low All Hostile Crosstalk of –83 dB @ 5 MHz
Reset Pin Allows Disabling of All Outputs (Connected
Excellent ESD Rating: Exceeds 4000 V Human Body
80-Lead TQFP Package (12 mm
APPLICATIONS
Routing of High Speed Signals Including:
AD8108: G = +1
AD8109: G = +2
8
Arrays
Buffered Inputs
Eight Output Amplifiers,
Drives 150
60 MHz 0.1 dB Gain Flatness
0.02%/0.02 Differential Gain/Differential Phase Error
–3 dB Bandwidth
Slew Rate
Through a Capacitor to Ground Provides “Power-
Model
Composite Video (NTSC, PAL, S, SECAM.)
Component Video (YUV, RGB)
Compressed Video (MPEG, Wavelet)
3-Level Digital Video (HDB3)
8 High Speed Nonblocking Switch Arrays
AD8108 (G = +1),
AD8109 (G = +2)
(R
On” Reset Capability)
8s to Create Larger Switch Arrays
L
= 150
16 Arrays See AD8116
Loads
)
AD8108
325 MHz
400 V/ s
12 mm)
AD8109
250 MHz
480 V/ s
8 Switch
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
phase of better than 0.02% and 0.02 respectively along with
0.1 dB flatness out to 60 MHz make the AD8108/AD8109 ideal
for video signal switching.
The AD8108 and AD8109 include eight independent output
buffers that can be placed into a high impedance state for paral-
leling crosspoint outputs so that off channels do not load the
output bus. The AD8108 has a gain of +1, while the AD8109
offers a gain of +2. They operate on voltage supplies of
while consuming only 45 mA of idle current. The channel switch-
ing is performed via a serial digital control (which can accommo-
date “daisy chaining” of several devices) or via a parallel control
allowing updating of an individual output without re-programing
the entire array.
The AD8108/AD8109 is packaged in an 80-lead TQFP package
and is available over the extended industrial temperature range
of –40 C to +85 C.
8 INPUTS
325 MHz, 8
UPDATE
DATA IN
RESET
CLK
CE
AD8108/AD8109
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3
World Wide Web Site: http://www.analog.com
8
PARALLEL LATCH
32-BIT SHIFT REGISTER
Crosspoint Switches
PARALLEL LOADING
4:8 DECODERS
AD8108/AD8109*
DECODE
SWITCH
MATRIX
WITH 4-BIT
32
32
64
8 Buffered Video
OUTPUT
BUFFER
G = +1,
G = +2
© Analog Devices, Inc., 1997
8
A0
A1
A2
DATA OUT
8 OUTPUTS
5 V

Related parts for AD8109

AD8109 Summary of contents

Page 1

... The AD8108 has a gain of +1, while the AD8109 offers a gain of +2. They operate on voltage supplies of while consuming only idle current. The channel switch- ing is performed via a serial digital control (which can accommo- date “ ...

Page 2

... AVCC, Outputs Disabled AVEE, Outputs Enabled, No Load AVEE, Outputs Disabled DVCC f = 100 kHz MHz Operating (Still Air) Operating (Still Air) –2– unless otherwise noted AD8108/AD8109 Typ Max Units 325/250 MHz 140/160 MHz 5 ns 400/480 ...

Page 3

... Figure 1. Timing Diagram, Serial Mode Table I. Logic Levels RESET, SER/PAR CLK, DATA IN, CE, UPDATE DATA OUT DATA OUT 2.7 V min 0.5 V max 20 A max –3– AD8108/AD8109 Limit Min Typ Max 20 100 20 100 0 50 180 8 6.4 100 200 OUT00 (D0 ...

Page 4

... AD8108/AD8109 TIMING CHARACTERISTICS (Parallel) Parameter Data Setup Time CLK Pulsewidth Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulsewidth Propagation Delay, UPDATE to Switch On or Off CLK, UPDATE Rise and Fall Times RESET Time 1 CLK 0 1 D0–D3 A0– LATCHED ...

Page 5

... ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Internal Power Dissipation AD8108/AD8109 80-Lead Plastic TQFP (ST 2.6 W Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range . . . . . . . . . . . . – +125 C Lead Temperature Range (Soldering 10 sec +300 C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only ...

Page 6

... AD8108/AD8109 CE UPDATE CLK DATA Data D3 PARALLEL DATA D2 (OUTPUT ENABLE) D3 SER/PAR DATA (SERIAL) CLK CLK CLK CE UPDATE OUT0 EN OUT1 EN OUT2 EN A0 OUT3 EN A1 ...

Page 7

... Parallel Data Input, TTL Compatible (Input Select). Parallel Data Input, TTL Compatible (Input Select MSB). Parallel Data Input, TTL Compatible (Output Enable). Not Connected ESD OUTPUT 1k ESD (AD8109 ONLY) AVEE b. Analog Output V CC ESD ESD DGND d. Logic Input Figure 5. I/O Schematics – ...

Page 8

... AGND 9 IN04 10 AGND 11 IN05 12 AGND 13 IN06 AGND 14 15 IN07 16 AGND 17 AVEE 18 AVCC 19 AVCC07 20 OUT07 CONNECT PIN CONFIGURATION PIN 1 IDENTIFIER AD8108/AD8109 TOP VIEW (Not to Scale) –8– DATA OUT 58 CLK 57 DATA IN 56 UPDATE 55 SER/PAR ...

Page 9

... REV. 0 0.4 0.3 0.2 0.1 0 200mV p-p –0.1 –0.2 –0.3 –0.4 100M 1G Figure 9. AD8108 Step Response, 100 mV Step 100 200 Figure 10. AD8108 Step Response Step 3RD HARMONIC 10M 100M –9– AD8108/AD8109 +50mV +25mV 0 –25mV –50mV 10ns/DIV +1.0V +0.5V 0 –0.5V –1.0V 10ns/DIV 2V STEP R = 150 L 0.2 0.1 0 –0.1 – ...

Page 10

... Figure 14. AD8109 Distortion vs. Frequency 0.4 0.3 0.2 0.1 200mV p-p 0 –0.1 –0.2 –0.3 –0.4 100M 1G Figure 15. AD8109 Step Response, 100 mV Step ALL HOSTILE 100M 200M Figure 16. AD8109 Step Response Step 3RD HARMONIC 10M 100M –10– +50mV +25mV 0 –25mV –50mV 10ns/DIV +1.0V +0.5V 0 –0.5V –1.0V 10ns/DIV 2V STEP RTO ...

Page 11

... Figure 22. AD8108 Off Isolation, Input-Output 1k 100 10 1 0.1 100 500 100k Figure 23. AD8108 Output Impedance, Enabled –11– AD8108/AD8109 5 SWITCHING BETWEEN TWO INPUTS 4 3 UPDATE INPUT TYPICAL VIDEO OUT (RTO) 0 –10 50ns/DIV p ...

Page 12

... FREQUENCY – Hz Figure 24. AD8109 PSRR vs. Frequency 100 56.3 31.6 17.8 10 5.63 3.16 10 100 1k 10k FREQUENCY – Hz Figure 25. AD8109 Voltage Noise vs. Frequency 100k 10k 1k 100 1 100k 1M 10M FREQUENCY – Hz Figure 26. AD8109 Output Impedance, Disabled 1M 10M Figure 27. AD8109 Switching Transient (Glitch) –40 –50 –60 – ...

Page 13

... Figure 34. AD8108 Offset Voltage Distribution 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 100M 1G 3G –60 Figure 35. AD8108 Offset Voltage Drift vs. Temperature (Normalized at +25 C) –13– AD8108/AD8109 V OUT 1 0 INPUT 1 AT +1V –1 INPUT 0 AT –1V 5 UPDATE 0 50ns/DIV Figure 33. AD8108 Switching Time –0.010 0.000 0.010 OFFSET VOLTAGE – Volts – ...

Page 14

... FREQUENCY – Hz Figure 36. AD8109 Input Impedance vs. Frequency V = 100mV 150 –2 –4 –6 –8 30k 100k 1M 10M FREQUENCY – Hz Figure 37. AD8109 Frequency Response vs. Capacitive Load V = 100mV IN 0 150 L 0 18pF L 0.2 0 12pF L –0.1 –0.2 –0.3 –0.4 30k 100k ...

Page 15

... THEORY OF OPERATION: The AD8108 (G = +1) and AD8109 (G = +2) share a common core architecture consisting of an array of 64 transconductance (gm) input stages organized as eight 8:1 multiplexers with a common, 8-line analog input bus. Each multiplexer is basically a folded-cascode high impedance voltage feedback amplifier with eight input stages. The input stages are NPN differential ...

Page 16

... For devices that will be used to drive a terminated cable with its outputs, the AD8109 can be used. This device has a built-in gain of two that eliminates the need for a gain-of-two buffer to drive a video line. Because of the presence of the feedback net- work in these devices, the disabled output impedance is about 1 k ...

Page 17

... The excellent video specifications of the AD8108/AD8109 make them ideal candidates for creating composite video crosspoint 8 8 switches. These can be made quite dense by taking advantage 8 of the AD8108/AD8109’s high level of integration and the fact R 8 TERM that composite video requires only one crosspoint channel per system video channel. There are, however, other video formats OUT 16– ...

Page 18

... Areas of Crosstalk For a practical AD8108/AD8109 circuit required that it be mounted to some sort of circuit board in order to connect it to power supplies and measurement equipment. Great care has been taken to create a characterization board (also available as an evaluation board) that adds minimum crosstalk to the intrin- sic device. This, however, raises the issue that a system’ ...

Page 19

... As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can be- come extremely large. For example, in the case of the 8 8 matrix of the AD8108/AD8109, we can examine the number of crosstalk terms that can be considered for a single channel, say IN00 input. IN00 is programmed to connect to one of the AD8108/AD8109 outputs where the measurement can be made ...

Page 20

... The areas that must be carefully detailed are grounding, shielding, signal routing and supply bypassing. The packaging of the AD8108/AD8109 is designed to help keep the crosstalk to a minimum. Each input is separated from each other input by an analog ground pin. All of these AGNDs should be directly connected to the ground plane of the circuit board ...

Page 21

... DGND DVCC DVCC AVCC 1 INPUT 00 2 AGND 3 INPUT 01 4 AGND 5 INPUT 02 6 AGND 7 INPUT 03 8 AGND AD8108 OR AD8109 9 INPUT 04 10 AGND 11 INPUT 05 12 AGND 13 INPUT 06 14 AGND 15 INPUT 07 16 AGND 59 DATA OUT 57 DATA Figure 46. Evaluation Board Schematic – ...

Page 22

... AD8108/AD8109 Figure 47. Component Side Silkscreen Figure 48. Board Layout (Component Side) –22– REV. 0 ...

Page 23

... REV. 0 Figure 49. Board Layout (Signal Layer) Figure 50. Board Layout (Power Plane) –23– AD8108/AD8109 ...

Page 24

... AD8108/AD8109 Optimized for video applications, all signal inputs and outputs are terminated with 75 resistors. Stripline techniques are used to achieve a characteristic impedance on the signal input and output lines also Figure 52 shows a cross-section of one of the input or output tracks along with the arrangement of the PCB layers ...

Page 25

... CLK line on the evaluation board to ground. A pad has been provided on the solder-side of the evaluation board to allow this capacitor to be soldered into place. Depending upon the overshoot from the printer port, this capacitor may need large as 0.01 F. AD8108/AD8109 Figure 54. Evaluation Board Control Panel –25– AD8108/AD8109 ...

Page 26

... AD8108/AD8109 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead Plastic TQFP (ST-80A) 0.559 (14.20) 0.543 (13.80) 0.063 (1.60) MAX 0.476 (12.10) 0.469 (11.90) 0.030 (0.75) 80 0.020 (0.50) 1 SEATING PLANE TOP VIEW (PINS DOWN) 0.003 (0.08) 20 MAX 21 0.006 (0.15) 0.002 (0.05) 0.020 (0.50) 0.011 (0.27) BSC 0.007 (0.17) 0.057 (1.45) 0.053 (1.35) –26– REV. 0 ...

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