SPCE061A Sunplus Technology Co., Ltd., SPCE061A Datasheet - Page 7

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SPCE061A

Manufacturer Part Number
SPCE061A
Description
16-bit sound controller with 32k x 16 flash memory
Manufacturer
Sunplus Technology Co., Ltd.
Datasheet

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FUNCTIONAL DESCRIPTIONS
5.1. CPU
The SPCE061A is equipped with a 16-bit
16-bit
micro-n-SP.
(General-purpose registers), PC (Program Counter), SP (Stack
Pointer), Base Pointer (BP) and SR (Segment Register). The
interrupts include three FIQs (Fast Interrupt Request) and eight
IRQs (Interrupt Request), plus one software-interrupt, BREAK.
5.2.2. Flash memory
Flash memory ($008000 ~ $00FFFF) is a high-speed memory with
access speed of two CPU clock cycles. FLASH erase and
program functions must be used in IDE tools.
5.3. PLL, Clock, Power Mode
5.3.1. PLL (Phase Lock Loop)
The purpose of PLL is to provide a base frequency (32768Hz) and
to pump the frequency from 20.48MHz to 49.152MHz for system
clock (Fosc). The default PLL frequency is 24.576MHz.
5.3.1.1. System clock
Basically, the system clock is provided by PLL and programmed
by the Port_SystemClock (W) to determine the frequency of clock
for system.
CPU clock is Fosc/8 if not specified. The initial CPU clock is
Fosc/8 after system wakes up and to be adjusted to desired CPU
clock by programming the Port_SystemClock (W). This avoids
Flash ROM reading failure when system wakes up.
5.3.1.2. 32768Hz RTC
The Real Time Clock (RTC) is normally used in watch, clock or
other time related products. A 2Hz-RTC (1/2 second) function is
loaded in SPCE061A. The RTC counts the timing as well as to
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
microprocessor
32768Hz X'tal
Eight registers are involved in
The default system clock Fosc = 24.576MHz and
b7,b6,b5 of P_SystemClock(W )($7013H)
System clock frequency selection
by SUNPLUS
System Clock generator
Phase Lock Loop
b7
(PLL)
b6
and
µ
b5
’nSP™, the newest
µ
’nSP™: R1 - R4
pronounced
24.576MHz(default)
as
32.768MHz
49.152MHz
20.48MHz
40.96MHz
PLL OUT
FOSC
7
Moreover, a high performance hardware multiplier with the
capability of FIR filter is also built in to reduce the software
multiplication loading.
5.2. Memory
5.2.1. SRAM
The amount of SRAM is 2K-word (including Stack), ranged from
$0000 through $07FF with access speed of two CPU clock cycles.
wake CPU up whenever RTC occurs.
generated each 0.5 seconds, time can be traced by the numbers
of RTC occurrence. In addition, SPCE061A supports 32768Hz
oscillator in strong mode and auto_weak mode. In strong mode,
32768Hz OSC always runs at the highest power consumption. In
auto_weak mode, however, it runs in strong mode for the first 7.5
seconds and changes back to auto_weak mode automatically to
save powers.
5.4. Power Savings Mode
The SPCE061A also offers a power savings mode (standby mode)
for low power application needs.
desired key wakeup port(IOA[7:0]) must be configured to input first.
And read the Port_IOA_Latch(R) to latch the IOA state before
entering the standby mode.
corresponding interrupt source(s) for wakeup. After that, stop the
CPU clock by writing the STOP CLOCK Register (b0~b2 of
Port_SystemClock (W)) to enter standby mode. In such mode,
SRAM and I/Os remain in the previous states till CPU being
awoken. The wakeup sources in SPCE061A include Port IOA7 -
0 and IRQ1 - IRQ6. After SPCE061A is awoken, the CPU will
continue to execute the program. Programmer can also enable
or disable the 32768Hz OSC when CPU is in standby mode.
of P_SystemClock(W )($7013H)
CPU clock frequency selection
n:1,2,4,8,16,32,64
Fosc/n
b2 b1 b0
Also remember to enable the
To enter standby mode, the
SPCE061A
(Default : Fosc/8)
Preliminary Version: 0.1
P
P
CPU Clock
Since the RTC is
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