LM3S1607 Luminary Micro, Inc, LM3S1607 Datasheet - Page 262
LM3S1607
Manufacturer Part Number
LM3S1607
Description
Lm3s1607 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1607.pdf
(548 pages)
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Reset
Reset
Type
Type
General-Purpose Input/Outputs (GPIOs)
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
Offset 0x514
Type R/W, reset 0x0000.0000
262
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
RO
RO
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 261).
30
14
0
0
RO
RO
29
13
reserved
0
0
Name
PDE
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0x00
0
9
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Pad Weak Pull-Down Enable
A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n]
enables. The change is effective on the second clock cycle after the
write.
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
PDE
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
June 02, 2008
R/W
RO
16
0
0
0
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