IDT723642L15PF IDT, Integrated Device Technology Inc, IDT723642L15PF Datasheet - Page 12

• Manufacturer Part Number: IDT723642L15PF
• Description: IC FIFO SYNC 2048X36 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723642L15PF

• Function: Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 72Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 1Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723642L15PF

full-2. From the time a word is read from a FIFO, its previous memory location
is ready to be written in a minimum of two cycles of the Input Ready flag
synchronizing clock. Therefore, an Input Ready flag is LOW if less than two
cycles of the Input Ready flag synchronizing clock have elapsed since the next
memory write location has been read. The second LOW-to-HIGH transition on
the Input Ready flag synchronizing Clock after the read sets the Input Ready
flag HIGH.
begins the first synchronization cycle of a read if the clock transition occurs at
time t
be the first synchronization cycle (see Figures 10 and 11 for timing diagrams).
ALMOST-EMPTY FLAGS (AEA, AEB)
data from its array. The state machine that controls an Almost-Empty flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
TABLE 4 — FIFO1 FLAG OPERATION
TABLE 5 — FIFO2 FLAG OPERATION
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
operation necessary), it is not included in the FIFO memory count.
programmed from port A.
operation necessary), it is not included in the FIFO memory count.
programmed from port A.
A LOW-to-HIGH transition on an Input Ready flag synchronizing clock
SKEW1
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
(X2+1) to [256-(Y2+1)]
(X1+1) to [256-(Y1+1)]
(256-Y2) to 255
(256-Y1) to 255
IDT723622
IDT723622
or greater after the read. Otherwise, the subsequent clock cycle can
1 to X2
1 to X1
256
256
0
0
(3)
(3)
Number of Words in FIFO
Number of Words in FIFO
(X2+1) to [512-(Y2+1)]
(X1+1) to [512-(Y1+1)]
(512-Y2) to 511
(512-Y1) to 511
IDT723632
IDT723632
1 to X2
1 to X1
512
512
0
0
(3)
(3)
(1,2)
(1,2)
(X2+1) to [1,024-(Y2+1)]
(X1+1) to [1,024-(Y1+1)]
(1,024-Y2) to 1,023
(1,024-Y1) to 1,023
IDT723642
IDT723642
1 to X2
1 to X1
1,024
1,024
12
0
0
almost-empty state is defined by the contents of register X1 for AEB and register
X2 for AEA. These registers are loaded with preset values during a FIFO reset
or programmed from port A (see Almost-Empty flag and Almost-Full flag offset
programming section). An Almost-Empty flag is LOW when its FIFO contains
X or less words and is HIGH when its FIFO contains (X+1) or more words. A
data word present in the FIFO output register has been read from memory.
clock are required after a FIFO write for its Almost-Empty flag to reflect the new
level of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more
words remains LOW if two cycles of its synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An Almost-Empty flag
is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after
the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of
an Almost-Empty flag synchronizing clock begins the first synchronization cycle
if it occurs at time t
Otherwise, the subsequent synchronizing clock cycle may be the first synchro-
nization cycle. (See Figures 12 and 13).
(3)
(3)
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing
SKEW2
ORA
ORB
H
H
H
H
H
H
H
H
L
L
Synchronized
or greater after the write that fills the FIFO to (X+1) words.
Synchronized
to CLKA
to CLKB
COMMERCIAL TEMPERATURE RANGE
AEA
AEB
H
H
H
H
H
H
L
L
L
L
AFB
AFA
H
H
H
H
H
H
L
Synchronized
L
Synchronized
L
L
to CLKB
to CLKA
IRB
IRA
H
H
H
H
H
H
H
H
L
L