IDT723642L15PF IDT, Integrated Device Technology Inc, IDT723642L15PF Datasheet - Page 21

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IDT723642L15PF

Manufacturer Part Number
IDT723642L15PF
Description
IC FIFO SYNC 2048X36 120QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet

Specifications of IDT723642L15PF

Function
Synchronous
Memory Size
72K (2K x 36)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
120-TQFP, 120-VQFP
Configuration
Dual
Density
72Kb
Access Time (max)
10ns
Word Size
36b
Organization
1Kx36x2
Sync/async
Synchronous
Expandable
No
Bus Direction
Bi-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
400mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
120
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
723642L15PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT723642L15PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT723642L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642.
CLKB
CLKA
CLKA
CLKB
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTES:
1. t
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
ENA
AEA
AFA
ENB
ENB
ENA
and rising CLKB edge is less than t
SKEW2
and rising CLKA edge is less than t
SKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge
is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
X2 Words in FIFO2
[D-(Y1+1)] Words in FIFO1
t
EN2S
t
ENS2
SKEW2
SKEW2
, then AFA may transition HIGH one CLKA cycle later than shown.
, then AEA may transition HIGH one CLKA cycle later than shown.
t
t
SKEW2
ENH
t
ENH
t
PAF
Figure 13. Timing for AEA
Figure 14. Timing for AFA
(1)
1
t
ENS2
AEA
AEA
AEA
AEA when FIFO2 is Almost-Empty
AFA
AFA
AFA when FIFO1 is Almost-Full
AFA
21
t
SKEW2
t
ENH
(D-Y1) Words in FIFO1
2
(1)
t
PAE
1
COMMERCIAL TEMPERATURE RANGE
(X2+1) Words in FIFO2
t
ENS2
2
t
PAF
t
ENH
t
PAE
3022 drw 15
3022 drw 16

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