LM3S6110 Luminary Micro, Inc, LM3S6110 Datasheet - Page 395
LM3S6110
Manufacturer Part Number
LM3S6110
Description
Lm3s6110 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S6110.pdf
(472 pages)
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Reset
Reset
Type
Type
PWM0 Load (PWM0LOAD)
Base 0x4002.8000
Offset 0x050
Type R/W, reset 0x0000.0000
July 25, 2008
Bit/Field
31:16
15:0
R/W
RO
31
15
0
0
R/W
Register 14: PWM0 Load (PWM0LOAD), offset 0x050
This register contains the load value for the PWM counter. Based on the counter mode, either this
value is loaded into the counter after it reaches zero, or it is the limit of up-counting after which the
counter decrements back to zero.
If the Load Value Update mode is immediate, this value is used the next time the counter reaches
zero; if the mode is synchronous, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 380).
If this register is re-written before the actual update occurs, the previous value is never used and is
lost.
RO
30
14
0
0
R/W
reserved
RO
29
13
0
0
Name
Load
R/W
RO
28
12
0
0
R/W
RO
27
11
0
0
Type
R/W
RO
R/W
RO
26
10
0
0
Reset
0x00
R/W
RO
25
0
9
0
0
Preliminary
R/W
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Counter Load Value
The counter load value.
reserved
Load
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
LM3S6110 Microcontroller
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
395
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