MT90826AL1 Zarlink Semiconductor, Inc., MT90826AL1 Datasheet
MT90826AL1
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MT90826AL1 Summary of contents
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... Timing Unit PLLV PLLV DD Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. MT90826AL MT90826AG MT90826AV MT90826AL1 Applications • Medium switching platforms • CTI application • Voice/data multiplexer • Digital cross connects • ...
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Description The MT90826 Quad Digital Switch has a non-blocking switch capacity of 4,096 x 4,096 channels at a serial bit rate of 8.192 Mbps or 16.384 Mbps, 2,048 x 2,048 channels at 4.096 Mbps and 1024 x 1024 channels at ...
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Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Stream Usage under Various Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Changes Summary The following table captures the changes from the April 2005 issue. Page 26 Figure 6 “Examples for Input Offset Delay Timing” 30 Section 9.0 Initialization of the MT90826 37 AC Electrical Characteristics - Serial Streams for ST-BUS. 37 ...
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NC 121 STo22 STo23 123 VSS VDD 125 STi24/FEi24 STi25/FEi25 127 STI26/FEi26 STi27/FEi27 129 VSS STo24 131 STo25 STo26 133 STo27 VSS 135 VDD STi28/FEi28 137 STi29/FEi29 STi30/FEi30 139 STi31/FEi31 VSS 141 STo28 STo29 143 STo30 ...
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A STi26 STi24 STo20 B STi27 STi25 STo21 C STo26 STo25 STo23 D STo27 STo24 STo22 E STi30 STi28 NC F STi31 STi29 NC G STo28 STo29 D0 H STo30 STo31 ...
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PINOUT DIAGRAM: (as viewed through top of package) A1 corner identified by metallized marking, mould indent, ink dot or right-angled corner STo23 STo20 STi21 B STo22 STo21 STi23 C STi26 STi25 STo24 D STi27 STi24 STo25 ...
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Pin Description Pin # MQFP Pin # PBGA 12,22,33,54, D5,D6,D7,D8,D9, 66,77,90,101, E4,E10,F4, 112,125,136, F10,G4,G10, 147,157 H4,J4,J10,K5, K6,K7 11,21,32,45, D4,D10,E5,E6, 53,60,65,71, E7,E8,E9,F5, 76,84,89,95, F9,G5,G9,H5, 100,106,111, H9,H10,J5,J6, 117,124,130, J7,J8,J9,K4 135,141,146, 156 34 N11 35 M11 36 N12 37 N13 38 M12 42 ...
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Pin Description (continued) Pin # MQFP Pin # PBGA 44 L12 46 L13 47 K12 50 K10 K13 55 J13 56 H13 57 H12 58 G13 59 G12 67-70 F13,F12,E13,E12 78,79 B13,A13 82,83 A12,B12 91-94 C11,C10,C9,C8 102-105 ...
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Pin Description (continued) Pin # MQFP Pin # PBGA 148 - 153 G3,J1,H3,J2,J3,K1, 154,155 K2,K3 158 L2,M1,M2,M3,N1, 8,9 N2, M6,N6,N7,M7, N9,N10,M8,M9,L7 L8,M10,L9,L10 ...
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See Figure 7 “Examples for Frame Output Offset Timing”. Serial Interface Mode Input Stream 8 Mbps 16 Mbps 4 Mbps and ...
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A13 A12 A11 A10 ...
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This data will be output on the ST-BUS streams in every frame until the data is changed by the microprocessor. The three most significant bits of the connection memory controls the following for an ...
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Mbps and 4 Mbps mode (DR2=1, DR1=0, DR0=1) When the 2 Mbps and 4 Mbps mode is selected, the device is configured with 32-input/32-output data streams. STi0-15/STo0-15 have a data rate of 2 Mbps and STi16-31/STo16-31 have a data ...
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Stream Address (ST0-31) A13 A12 A11 A10 ...
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In the control register, a zero to one transition of the CBER bit resets the ...
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Read/Write Address: Reset Value BPD2 BPD1 BPD0 CPLL 0 Bit Name BPD2-0 Block Programming Data. These bits carry the value to be loaded into the connection memory block whenever the memory block ...
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Read/Write Address: Reset Value BPD2 BPD1 BPD0 CPLL 0 Bit Name 4 MS Memory Select. When 0, connection memory is selected for read or write operations. When 1, the data memory is selected for read ...
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Read/Write Address: Reset Value FE4 FE3 FE2 FE1 FE0 Bit Name FE4-0 Frame Evaluation Input Select. The binary value expressed in these bits refers to the frame evaluation inputs, FEi0 to FEi31. ...
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Frame Boundary F0i CLK (16.384 MHz) Internal master clock at 32 MHz Offset Value 0 1 FEi Input For 8 Mbps, 16 Mbps, 4&8 Mbps and 16&8 Mbps modes F0i CLK (16.384 MHz) Internal master clock at 16 MHz Offset ...
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Read/Write Address Reset value: 0000 IF33 IF32 IF31 IF30 IF23 IF73 IF72 IF71 IF70 IF63 IF113 IF112 IF111 IF110 IF103 IF153 IF152 IF151 IF150 IF143 IF193 IF192 IF191 IF190 IF183 IF233 ...
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Read/Write Address: Reset value IF33 IF32 IF31 IF30 IF23 IF73 IF72 IF71 IF70 IF63 IF113 IF112 IF111 IF110 IF103 IF153 IF152 IF151 IF150 IF143 IF193 IF183 IF192 IF191 IF190 IF233 IF232 IF231 IF230 IF223 IF272 IF271 ...
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Input Stream Offset No internal master clock shift (Default) + 0.5 internal master clock shift + 1.0 internal master clock shift + 1.5 internal master clock shift + 2.0 internal master clock shift + 2.5 internal master clock shift + ...
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F0i CLK (16.384 MHz) Internal master clock at 32 MHz 8Mbps STi Stream 8Mbps STi Stream denotes the 3/4 point of the 8M bps bit cell F0i CLK (16.384 MHz) Internal master clock at 32 MHz 16Mbps STi Stream Bit ...
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Read/Write Address: 000A 000B 000C 000D Reset value: 0000 OF71 OF70 OF61 OF60 OF51 OF50 OF151 OF150 OF141 OF140 OF131 OF130 OF231 OF230 OF221 OF220 OF211 OF210 OF311 OF310 OF301 OF300 OF291 OF290 Name (Note ...
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F0i CLK (16.384MHz) STo Stream STo Stream Figure 7 - Examples for Frame Output Offset Timing Read/Write Address: Reset value BSA4 BSA3 Bit Name BSA4 - BSA0 BER Input ...
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Memory Mapping The address bus on the microprocessor interface selects the internal registers and memories of the MT90826. If the A13 address input is low, then the registers are addressed by A12 to A0 according to Table 3. If ...
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Initialization of the MT90826 During power up, the TRST pin should be pulsed low, or held low continuously, to ensure that the MT90826 is in the normal functional mode pull-down resistor can be connected to the ...
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Instruction Register In accordance with the IEEE 1149.1 standard, the MT90826 uses public instructions. The JTAG Interface contains a three-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in ...
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Boundary Scan Bit 0 to Bit 165 Device Pin Tri-state Output Scan Control F0i CLK ODE STi0 STi1 STi2 STi3 STo0 7 STo1 9 STo2 11 STo3 13 STi4 STi5 STi6 STi7 STo4 19 STo5 21 STo6 23 STo7 25 ...
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Boundary Scan Bit 0 to Bit 165 Device Pin Tri-state Control STi28 STi29 STi30 STi31 STo28 91 ST029 93 ST030 95 STo31 102 D2 105 D3 108 D4 111 D5 114 D6 117 D7 120 D8 ...
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SAB SAB TM1 TM0 Bit Name 15-14 TM1-0 Mode Select Bits. TM1 TM0 13 OE Output Enable. This bit enables the drivers of STo pins on a per-channel basis. When 1, the ...
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Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any 3.3 V tolerant pin I/O (other than supply pins) 3 Voltage on any 5 V tolerant pin I/O (other than sup- ply pins) 4 Continuous Current at digital outputs ...
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AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels Characteristics 1 CMOS Threshold Voltage 2 CMOS Rise/Fall Threshold Voltage High 3 CMOS Rise/Fall Threshold Voltage Low AC Electrical Characteristics - Frame Pulse and CLK Characteristic 1 Frame pulse width 2 ...
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AC Electrical Characteristics - Serial Streams for ST-BUS Characteristic 1 Input Data Sample Point (Data rate of 16 Mbps) 2 Input Data Sample Point (Data rate of 8 Mbps) 3 Input Data Sample Point (Data rate of 4 Mbps) 4 ...
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FPW F0i t t FPS FPH t IDS_8 CLK (16.384 MHz) t SOD STo Bit 0, Last Channel STi Bit 0, Last Channel Figure 9 - ST-BUS Timing for Stream rate of 8.192 Mbps when CLK = 16.384 MHz ...
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FPW F0i t t FPS FPH CLK (16.384 MHz) t SOD STo Ch31 Bit 0 (2 Mbps) STi Ch31 Bit 0 (2 Mbps) Figure 12 - ST-BUS Timing for Stream rate of 2.048 Mbps when CLK = 16.384 MHz ...
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MT90826 ODE t t ODE ODE Valid Data STo HiZ HiZ Figure 15 - Output Driver Enable (ODE) 40 Zarlink Semiconductor Inc. Data Sheet ...
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AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 ...
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DS CS R/W A0-A7 D0-D15 READ D0-D15 WRITE DTA Figure 16 - Motorola Non-Multiplexed Bus Timing MT90826 t CSS t RWS t ADS Valid Address Valid Read Data t t DSW SWD Valid Write Data t DDR t AKD 42 ...
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Zarlink Semiconductor 2002 All rights reserved ISSUE 213834 ACN 213740 11Dec02 15Nov02 DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...