IDT72T36125L5BB IDT, Integrated Device Technology Inc, IDT72T36125L5BB Datasheet - Page 38
IDT72T36125L5BB
Manufacturer Part Number
IDT72T36125L5BB
Description
IC FIFO 524X18 5NS 240BGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Tr
Datasheet
1.IDT72T3645L6-7BB.pdf
(57 pages)
Specifications of IDT72T36125L5BB
Function
Asynchronous, Synchronous
Memory Size
9.4K (524 x 18)
Data Rate
83MHz
Access Time
5ns
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72T36125L5BB
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72T36125L5BB
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72T36125L5BBG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72T36125L5BBGI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72T36125L5BBI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH.
3. WCS = LOW.
NOTES:
1. t
2. LD = HIGH.
3. First data word latency = t
4. RCS is LOW.
Q
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
D
Q0 - Qn
D0 - Dn
WCLK
0
0
WCLK
WCS
RCLK
RCLK
rising edge of the RCLK and the rising edge of the WCLK is less than t
rising edge of WCLK and the rising edge of RCLK is less than t
WEN
SKEW1
WEN
SKEW1
RCS
REN
- D
- Q
REN
FF
EF
OE
n
n
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
t
ENS
t
t
ENS
ENS
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
t
RCSLZ
t
SKEW1
t
t
OLZ
ENH
SKEW1
t
REF
t
A
(1)
t
OE
+ 1*T
t
WCSS
t
ENH
t
SKEW1
t
RCLK
ENS
t
A
t
DS
1
D
(1)
+ t
Figure 11. Write Cycle and Full Flag Timing (IDT Standard Mode)
NO WRITE
0
REF.
NO OPERATION
t
t
DH
ENH
LAST WORD
1
2
t
WFF
SKEW1
t
DS
t
, then EF deassertion may be delayed one extra RCLK cycle.
t
OHZ
t
CLKH
t
SKEW1
DS
ENS
D
, then the FF deassertion may be delayed one extra WCLK cycle.
D
X
1
NO OPERATION
t
WFF
DATA READ
t
38
t
t
ENH
DH
WCSH
t
DH
t
CLK
2
t
CLKL
t
t
CLKH
ENS
t
REF
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
t
ENS
ENH
LAST WORD
t
A
1
NO WRITE
t
ENH
COMMERCIAL AND INDUSTRIAL
t
A
2
TEMPERATURE RANGES
NEXT DATA READ
WFF
REF
t
t
ENS
WFF
t
DS
). If the time between the
FEBRUARY 4, 2009
). If the time between the
D
0
D
X+1
t
REF
t
t
ENH
A
5907 drw16
t
DH
t
5907 drw17
WFF
D
1