CS4272 Cirrus Logic, CS4272 Datasheet

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CS4272

Manufacturer Part Number
CS4272
Description
24-Bit / 192 kHz Stereo Audio CODEC
Manufacturer
Cirrus Logic
Datasheet

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D/A Features
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Cirrus Logic, Inc.
www.cirrus.com
Control Data
Hardware or
High Performance
– 114 dB Dynamic Range
– -100 dB THD+N
Up to 192 kHz Sampling Rates
Differential Analog Architecture
Volume Control with Soft Ramp
– 1 dB Step Size
– Zero Crossing Click-free Transitions
Selectable Digital Filters
– Fast and Slow Roll Off
ATAPI Mixing Functions
Selectable Serial Audio Interface Formats
– Left Justified up to 24-bit
– I
– Right Justified 16-, 18-, 20-, and 24-Bit
Control Output for External Muting
Selectable 50/15 µs De-emphasis
I
2
Output
2
Reset
C/SPI
Serial
Audio
Serial
Audio
S up to 24-bit
Input
2.5 V to 5 V
24-Bit, 192 kHz Stereo Audio CODEC
Register / Hardware
Configuration
3.3 V to 5 V
Volume
Volume
Control
Control
DC Offset Calibration
DC Offset Calibration
Copyright © Cirrus Logic, Inc. 2005
High Pass Filter &
High Pass Filter &
(All Rights Reserved)
Interpolation
Interpolation
Selectable
Selectable
Filter
Filter
Internal Voltage
Reference
A/D Features
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System Features
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High Performance
– 114 dB Dynamic Range
– -100 dB THD+N
Up to 192 kHz Sampling Rates
Differential Analog Architecture
Multi-bit Delta Sigma Conversion
High-pass Filter or DC Offset Calibration
Low-Latency Digital Anti-alias Filtering
Automatic Dithering of 16-bit Data
Selectable Serial Audio Interface Formats
– Left Justified up to 24-bit
– I
Direct Interface with 5V to 2.5V Logic Levels
Internal Digital Loopback
On-chip Oscillator
Stand-Alone or Control Port Functionality
2
S up to 24-bit
Anti-Alias Filter
Anti-Alias Filter
Low-Latency
Low-Latency
∆Σ Modulator
∆Σ Modulator
Oscillator
Internal
5 V
Switched Capacitor
Switched Capacitor
DAC and Filter
DAC and Filter
Mute Control
Oversampling
Oversampling
External
Multibit
Multibit
ADC
ADC
CS4272
AUGUST '05
DS593F1
Left and
Right Mute
Controls
Left
Differential
Output
Right
Differential
Output
Left
Differential
Input
Right
Differential
Input

Related parts for CS4272

CS4272 Summary of contents

Page 1

... Volume Interpolation Control Filter High Pass Filter & DC Offset Calibration High Pass Filter & DC Offset Calibration Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) CS4272 24-bit 5 V Internal External Oscillator Mute Control Switched Capacitor ∆Σ Modulator DAC and Filter Switched Capacitor ∆ ...

Page 2

... Integrated level translators allow easy interfacing be- tween the CS4272 and other devices operating over a wide range of logic levels. An on-chip oscillator eliminates the need for an external crystal oscillator circuit. This can reduce overall design cost and conserve circuit board space ...

Page 3

... Internal Digital Loopback .................................................................................... 30 5.2.5 Dither for 16-Bit Data .......................................................................................... 30 5.2.6 Auto-Mute ........................................................................................................... 30 5.2.7 High Pass Filter and DC Offset Calibration ......................................................... 30 5.2.8 Interpolation Filter .............................................................................................. 31 5.2.9 De-Emphasis ...................................................................................................... 31 5.2.10 Oversampling Modes ........................................................................................ 31 5.3 De-Emphasis Filter .......................................................................................................... 31 5.4 Analog Connections ........................................................................................................ 32 5.4.1 Input Connections ............................................................................................... 32 5.4.2 Output Connections ............................................................................................ 33 5.5 Mute Control .................................................................................................................... 34 5.6 Synchronization of Multiple Devices ................................................................................ 34 5.7 Grounding and Power Supply Decoupling ....................................................................... 34 6. CONTROL PORT INTERFACE .............................................................................................. 35 DS593F1 CS4272 3 ...

Page 4

... Mode Control 2 - Address 07h ......................................................................................... 43 8.7.1 Digital Loopback (Bit 4) ....................................................................................... 43 8.7.2 AMUTEC = BMUTEC (Bit 3) ............................................................................... 43 8.7.3 Freeze (Bit 2) ...................................................................................................... 44 8.7.4 Control Port Enable (Bit 1) .................................................................................. 44 8.7.5 Power Down (Bit 0) ............................................................................................. 44 8.8 Chip ID - Register 08h ..................................................................................................... 44 8.8.1 Chip ID (Bits 7:4) ................................................................................................. 44 8.8.2 Chip Revision (Bits 3:0) ....................................................................................... 44 9. PARAMETER DEFINITIONS .................................................................................................. 45 10. PACKAGE DIMENSIONS ..................................................................................................... 46 11. APPENDIX ............................................................................................................................ 47 4 CS4272 DS593F1 ...

Page 5

... LRCK SCLK SDOUT SDIN DGND VD VL SCL/CCLK SDA/CDIN AD0/CS RST DS593F1 28-Pin TSSOP CS4272 BMUTEC AOUTB- AOUTB+ AOUTA+ AOUTA- AMUTEC FILT+ AGND VA AINB- AINB+ AINA+ AINA- VCOM 5 ...

Page 6

... Differential Analog Audio Output (Output) - The full scale differential output level is specified in the AOUTB+ 26, DAC Analog Characteristics specification table. AOUTB- 27 Channel B Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when 28 BMUTEC master clock to left/right clock frequency ratio is incorrect, or power-down. 6 CS4272 DS593F1 ...

Page 7

... MCLK LRCK SCLK SDOUT (M/S) SDIN DGND I2S/LJ RST DS593F1 28-Pin TSSOP CS4272 BMUTEC AOUTB- AOUTB+ AOUTA+ AOUTA- AMUTEC FILT+ AGND VA AINB- AINB+ AINA+ AINA- VCOM 7 ...

Page 8

... Differential Analog Audio Output (Output) - The full scale differential output level is specified in the AOUTB+ 26, Analog Characteristics specification table. AOUTB- 27 Channel B Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when 28 BMUTEC master clock to left/right clock frequency ratio is incorrect, or power-down. 8 CS4272 2 S format for the Serial Audio DS593F1 ...

Page 9

... Positive Logic VL 2.37 Commercial Grade T A Automotive Grade (GND = 0 V, All voltages with respect to ground.) (Note 1) Symbol Analog VA VL Logic VD Digital (Note GND-0 IND stg CS4272 Min Nom Max Units 5.0 5.25 V 3.1 3.3 5.25 V 3.3 5.25 V °C -10 - +70 °C -40 - +85 Min Typ Max Units -0 ...

Page 10

... Symbol Min A-Weighted 108 unweighted 105 unweighted 0 dB THD+N - kHz) ICGM V 0.91xVA FS (note 7) Z out but does not include attenuation due CS4272 (Notes Typ Max Unit 114 - dB 111 - -100 - - -51 - ...

Page 11

... Maximum Load Capacitance DS593F1 Symbol Min A-Weighted 106 unweighted 103 unweighted - 0 dB THD kHz) - ICGM - - V 0.91xVA FS (note out CS4272 (Notes Typ Max Unit 114 - dB 111 - -100 - -51 -43 dB 114 - dB 100 - dB 0 100 - ppm/°C 0.96xVA 1 ...

Page 12

... kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner 0 -0.01 .583 (Note 10 -0.01 dB corner corner 0 -0.01 .635 (Note 10 CS4272 Typ Max Unit - .454 Fs - .499 Fs - +0. 12/ ±0. ±0. ±0. .430 ...

Page 13

... kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner 0 -0.01 .792 (Note 10 -0.01 dB corner corner 0 -0.01 .868 (Note 10 CS4272 Typ Max Unit - 0.417 Fs - 0.499 Fs - +0. 6.5/ ±0. ±0. ±0. .296 ...

Page 14

... THD - - A-weighted 108 unweighted 105 - (Note 13) THD - - HPF enabled - HPF disabled - 1.07xVA (Note 14) 37 CMRR - CS4272 Typ Max Unit 114 - dB 111 - dB -100 - 114 - dB 111 - dB 108 - dB -100 - -97 ...

Page 15

... kHz A-weighted unweighted (Note 15) THD - 192 kHz A-weighted unweighted (Note 15) THD - HPF enabled HPF disabled 1.07xVA (Note 16) CMRR CS4272 Min Typ Max 106 114 - 103 111 - - -100 - -51 - 106 114 - 103 111 ...

Page 16

... Min Typ (Note 17 (Note 17) 0. 12/Fs gd (Note 17 (Note 17) 0. 9/Fs gd (Note 17 (Note 17) 0. (Note 18) 20 (Note 18 /Fs CS4272 Max Unit 0.47 Fs ±0.035 0.45 Fs ±0.035 0.24 Fs ±0.035 Deg DS593F1 ...

Page 17

... Input Leakage Current DS593F1 Symbol VL, VL, VL,VD VL (Power-Down Mode) - (Note 21) PSRR VCOM FILT+ Symbol (% CS4272 Min Typ Max - 41 0.025 - - 1. 433 510 - 305 358 - 0.48xVA - - 1 - ...

Page 18

... Single Speed Mode sclkw t Double Speed Mode sclkw t Quad Speed Mode sclkw t sclkh t sclkl t slr t sdo t sdis t sdih f osc CS4272 (Logic "0" = GND = 0 V; Min Typ Max 100 100 - 200 1.024 - 25.600 1.024 - 51.200 ...

Page 19

... LRCK O utput SCLK O utput SDO UT SDIN Figure 1. Master Mode Serial Audio Port Timing LRCK Input SCLK Input SDOUT SDIN DS593F1 t slr t sdo t sdis t t sclkh slr t sclkw t sdo t sdis Figure 2. Slave Mode Serial Audio Port Timing CS4272 t sdih t sclkl t sdih 19 ...

Page 20

... LSB MSB - Figure 3. Format 0, Left Justified up to 24-Bit Data + LSB MSB - Figure 4. Format 1, I² 24-Bit Data + CS4272 Right Channel + LSB Right Channel + LSB R ight Channel +6 ...

Page 21

... Repeated Start t high t t sud t sust low hdd Figure 6. I²C Mode Control Port Timing CS4272 Min Max Unit - 100 KHz 500 - ns 4.7 - µs 4.0 - µs 4.7 - µs 4.0 - µs 4.7 - µ µs 250 - ns ...

Page 22

... Figure 7. SPI Control Port Timing CS4272 Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ...

Page 23

... See "Master/Slave Mode Selection" SDOUT ( (I2S SDIN MCLK CS4272 SCLK LRCK AOUTA- AMUTEC AOUTA+ AOUTB- BMUTEC AOUTB+ DGND Figure 8. CS4272 Typical Connection Diagram CS4272 * + 2.5 V 0.1 µF 1 µF ¤ 47 kΩ Audio Data Processor Timing Logic & Clock Analog Conditioning & Mute 23 ...

Page 24

... VL on the SDOUT (M/S) pin. Configuration of clock ratios in each of these modes will be outlined in the Tables 3 and 4. 5.1.3 System Clocking The CS4272 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed modes as shown in Table 1 below. 5.1.3.1 Crystal Applications (XTI/XTO) An external crystal may be used in conjunction with the CS4272 to generate the master clock signal ...

Page 25

... Clock Ratio Selection Depending on the use of an external crystal, or whether the CS4272 is in Master or Slave Mode, different MCKL/LRCK and SCLK/LRCK ratios may be used. These ratios are shown in the Tables 3 and 4 below. Table 3. Clock Ratios - Stand Alone Mode With External Crystal Single Speed ...

Page 26

... Filter specifications can be found in Section 3. Plots of the data are contained in the “Appendix” on page 47. 5.1.8 Mode Selection & De-Emphasis The sample rate, Fs, can be adjusted from 4 kHz to 200 kHz. In Stand-Alone Mode, the CS4272 must be set to the proper mode via the mode pins, M1 and M0. De-emphasis, optimized for a 44.1 kHz sampling frequency, is avail- able. ...

Page 27

... SCLK be 64x Fs to maximize system performance. Configuration of clock ratios in each of these modes will be outlined in the Tables 8 and 9. In Control Port Mode the CS4272 will default to Slave Mode. The user may change this default setting by changing the status of the M/S bit in the Mode Control 1 register (01h). ...

Page 28

... To operate the CS4272 with an externally generated MCLK signal, no crystal should be used, XTI should be con- nected to ground and XTO should be left unconnected. In this configuration, MCLK is an input and must be driven externally with an appropriate speed clock. 5.2.3.2 Clock Ratio Selection Depending on the use of an external crystal, or whether the CS4272 is in Master or Slave Mode, different MCKL/LRCK and SCLK/LRCK ratios may be used ...

Page 29

... Slave Mode SCLK/LRCK LRCK 32, 64, 128 32, 48, 64, 96, 128 32, 64, 128 32, 48, 64, 96, 128 32, 64, 128 32, 64 32, 48, 64 32, 64 32, 48 32, 64 CS4272 Ratio1 Bit Ratio0 Bit ...

Page 30

... Internal Digital Loopback In Control Port Mode, the CS4272 supports an internal digital loopback mode in which the output of the ADC is rout the input of the DAC. This mode may be activated by setting the LOOP bit in the Mode Control 2 register (07h). When this bit is set, the status of the DAC_DIF(2:0) bits in register 01h will be disregarded by the CS4272. Any ...

Page 31

... See Table 13 for de-emphasis selection in Control Port Mode. 5.2.10 Oversampling Modes The CS4272 operates in one of three oversampling modes based on the input sample rate. Mode selection is de- termined by the M1 and M0 bits in the Mode Control 1 register. Single-Speed mode supports input sample rates kHz and uses a 128x oversampling ratio ...

Page 32

... Figure 13 shows the full-scale analog input levels. 10 µF AIN+ 10 kΩ 0.01 µF 10 kΩ AIN- 10 µF Figure 12. CS4272 Recommended Analog Input Buffer 3.9 V 2.5 V 1.1 V 3.9 V 2.5 V 1.1 V Full-Scale Input Level= (AIN+) - (AIN-)= 5.6 Vpp 32 634 Ω ...

Page 33

... AC loads on the AOUT+ and AOUT- differential output pins. It also shows an AC coupling configuration which minimizes the number of required AC coupling capacitors. The CS4272 does not include phase or amplitude compensation for an external filter, and therefore the DAC system phase and amplitude response will be dependent on the external analog circuitry. Figure 15 shows the full-scale an- alog output levels ...

Page 34

... In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS4272’s in the system. If only one MCLK source is needed, one solution is to place one CS4272 in Master Mode, and slave all of the other CS4272’s to the one master ...

Page 35

... SPI Mode In SPI mode the CS4272 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller and the chip address is 0010000. All control signals are inputs and data is clocked in on the rising edge of CCLK. ...

Page 36

... VA or AGND as required. The upper 6 bits of the 7-bit address field must be 001000. To communicate with the CS4272, the LSB of the chip address field, which is the first byte sent to the CS4272, should match the setting of the AD0 pin. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written ...

Page 37

... ATAPI3 VOL5 VOL4 VOL3 VOL5 VOL4 VOL3 ADC_DIF0 MUTEA LOOP MUTECA=B FREEZE PART1 PART0 REV3 CS4272 DAC_DIF2 DAC_DIF1 DAC_DIF0 M RMP_DN INV_B ATAPI2 ATAPI1 VOL2 VOL1 VOL2 VOL1 MUTEB HPFDisableA HPFDisableB ...

Page 38

... Table 12. DAC Digital Interface Formats Description Left Justified 24-bit data (default 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data Right Justified, 20-bit Data Right Justified, 18-bit Data Reserved Reserved CS4272 DAC_DIF2 DAC_DIF1 DAC_DIF0 Format Figure ...

Page 39

... DS593F1 DEM0 RMP_UP Table 13. De-Emphasis Mode Selection DEM0 Description 0 0 Disabled (default 44.1 kHz de-emphasis kHz de-emphasis kHz de-emphasis Gain dB T1=50 µs 0dB F1 F2 3.183 kHz 10.61 kHz Figure 19. De-Emphasis Curve CS4272 2 1 RMP_DN INV_A INV_B µs Frequency 0 39 ...

Page 40

... The requested level change will occur after a time-out period between 512 and 1024 sample periods (10 21 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon ZeroCross ATAPI3 CS4272 ATAPI2 ATAPI1 ATAPI0 DS593F1 ...

Page 41

... Table 14. Soft Cross or Zero Cross Mode Selection Soft 8.3.3 ATAPI Channel Mixing and Muting (Bits 3:0) Function: The CS4272 implements the channel mixing functions of the ATAPI CD-ROM specification. See Table 15 on page 42 Left Channel Audio Data Right Channel Audio Data DS593F1 ZeroCross Mode ...

Page 42

... VOL4 VOL3 Decimal Value CS4272 AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/ VOL2 VOL1 VOL0 Volume Setting 0 dB -20 dB -40 dB -60 dB -90 dB DS593F1 0 ...

Page 43

... AMUTEC and BMUTEC are valid. DS593F1 ADC_DIF MUTEA Table 17. ADC Digital Interface Formats Description 24-bit data LOOP MUTECA=B CS4272 MUTEB HPFDisableA HPFDisableB Format Figure FREEZE CPEN ...

Page 44

... Chip ID - Register 08h B7 B6 PART3 PART2 PART1 This is a Read-Only register. 8.8.1 Chip ID (Bits 7:4) Function: Chip ID code for the CS4272. Permanently set to 0000b (0h). 8.8.2 Chip Revision (Bits 3:0) Function: Chip Revision code for the CS4272. Revision A is coded as 0000b (0h). Revision B is coded as 0000b (0h ...

Page 45

... The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS593F1 CS4272 45 ...

Page 46

... NOM MAX MIN -- 0.47 -- 0.006 0.05 0.035 0.04 0.80 0.012 0.19 0.386 BSC 9.60 BSC 0.256 6.30 0.177 4. 0.029 0.50 4° 8° 0° JEDEC #: MO-153 Controlling Dimension is Millimeters. Symbol θ 28-TSSOP JA θ JC CS4272 1 E1 END VIEW L NOTE MILLIMETERS NOM MAX -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 2,3 9.70 BSC 9.80 BSC 1 6.40 6.50 4.40 4.50 1 0.65 BSC -- 0.60 0.75 4° 8° Min Typ ...

Page 47

... DS593F1 100 120 0.4 0.42 0.8 0.9 1 Figure 22. DAC Single Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 24. DAC Single Speed (fast) Passband Ripple 100 120 0.8 0.9 1 0.4 0.42 Figure 26. DAC Single Speed (slow) Transition Band CS4272 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.6 0.5 0.6 47 ...

Page 48

... Figure 28. DAC Single Speed (slow) Passband Ripple 100 120 0.4 0.42 0.8 0.9 1 Figure 30. DAC Double Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 32. DAC Double Speed (fast) Passband Ripple CS4272 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) DS593F1 0.5 0.6 0.5 ...

Page 49

... DS593F1 100 120 0.2 0.7 0.8 0.9 1 Figure 34. DAC Double Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 Figure 36. DAC Double Speed (slow) Passband Ripple 100 120 0.2 0.7 0.8 0.9 1 Figure 38. DAC Quad Speed (fast) Transition Band CS4272 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.35 0.8 49 ...

Page 50

... Figure 43. DAC Quad Speed (slow) Transition Band (detail) 50 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 0 0.52 0.53 0.54 0.55 Figure 40. DAC Quad Speed (fast) Passband Ripple 100 120 0.1 0.2 0.7 0.8 0.9 1 Figure 42. DAC Quad Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.02 Figure 44. DAC Quad Speed (slow) Passband Ripple CS4272 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.04 0.06 0.08 0.1 Frequency(normalized to Fs) DS593F1 0.9 0.12 ...

Page 51

... Figure 46. ADC Single Speed Mode Transition Band 0.10 0.08 0.05 0.03 0.00 -0.03 -0.05 -0.08 -0.10 0.52 0.53 0.54 0.55 0.00 0.05 0.10 Figure 48. ADC Single Speed Mode Passband Ripple 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.43 0.45 0.7 0.8 0.9 1.0 Figure 50. ADC Double Speed Mode Transition Band CS4272 0.46 0.48 0.50 0.52 0.54 0.56 0.58 Frequency (normalized to Fs) 0.15 0.20 0.25 0.30 0.35 0.40 0.45 Frequency (normalized to Fs) 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 Frequency (normalized to Fs) 0.60 0.50 0.70 51 ...

Page 52

... Figure 52. ADC Double Speed Mode Passband Ripple 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0.2 0.25 0.3 0.7 0.8 0.9 1.0 Figure 54. ADC Quad Speed Mode Transition Band 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.45 0.5 0.55 0.6 0.00 0.05 Figure 56. ADC Quad Speed Mode Passband Ripple CS4272 0.10 0.15 0.20 0.25 0.30 0.35 0.40 Frequency (normalized to Fs) 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 Frequency (normalized to Fs) 0.10 0.15 0.20 Frequency (normalized to Fs) DS593F1 0.45 0.50 0.8 0.25 ...

Page 53

... Updated the DC Electrical Characteristics table on page 17. - Corrected error in the SCLK Period units shown in the Switching Character- istics - Serial Audio Port table on page 18. - Corrected error in the Memory Address Pointer table on page 36. - Updated Chip ID register description on page 44. CS4272 53 ...

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