AD9516-5 Analog Devices, Inc., AD9516-5 Datasheet - Page 8
AD9516-5
Manufacturer Part Number
AD9516-5
Description
14-output Clock Generator
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD9516-5.pdf
(76 pages)
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AD9516-5
Parameter
1
2
3
4
5
Timing Diagrams
This is the difference between any two similar delay paths while operating at the same voltage and temperature.
Corresponding CMOS drivers set to OUTxA for noninverting, and OUTxB for inverting, x = 6, 7, 8, or 9.
The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.
Incremental delay; does not include propagation delay.
All delays between zero scale and full scale can be estimated by linear interpolation.
Delay Variation with Temperature
CLK
Short Delay Range
Long Delay Range
Zero Scale
Full Scale
Zero Scale
Full Scale
DIFFERENTIAL
20%
Figure 2. CLK/ CLK to Clock Output Timing, DIV = 1
t
LVDS
t
CMOS
80%
Figure 3. LVPECL Timing, Differential
t
t
PECL
RP
5
5
t
CLK
LVPECL
t
FP
Min
Rev. 0 | Page 8 of 76
Typ
0.23
−0.02
0.3
0.24
Max
Unit
ps/°C
ps/°C
ps/°C
ps/°C
DIFFERENTIAL
SINGLE-ENDED
20%
20%
Figure 5. CMOS Timing, Single-Ended, 10 pF Load
80%
80%
Test Conditions/Comments
Figure 4. LVDS Timing, Differential
t
t
RC
RL
10pF LOAD
CMOS
LVDS
t
t
FL
FC
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