HEF4013BT,652 NXP Semiconductors, HEF4013BT,652 Datasheet - Page 10

• Manufacturer Part Number: HEF4013BT,652
• Description: IC FLIP FLOP DUAL D TYPE 14SOIC
• Manufacturer: NXP Semiconductors
• Series: 4000Br
• Type: D-Typer

Specifications of HEF4013BT,652

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Function: Set(Preset) and Reset
• Output Type: Differential
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 40MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 3.4mA, 3.4mA
• Voltage - Supply: 3 V ~ 15 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: HE4000B
• Logic Type: D-Type Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 90 ns
• High Level Output Current: - 4.2 mA
• Low Level Output Current: 4.2 mA
• Supply Voltage (max): 15 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 3 V
• Technology: CMOS
• Number Of Bits: 2
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 3.3/5/9/12V
• Package Type: SO
• Frequency (max): 40MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 15V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1685-5; 933372660652; HEF4013BTD

Philips Semiconductors
January 1995
handbook, full pagewidth
In the waveforms above the active transition of the clock input is going from LOW to HIGH and
the active level of the forcing signals (SET, CLEAR and PRESET) is HIGH.
The actual direction of the active transition of the clock input and the actual active levels of the
forcing signals are specified in the individual device data sheet.
Fig.7 Set-up times, hold times, recovery times and propagation delays for sequential logic circuits.
OUTPUT
PRESET
CLOCK
RESET,
INPUT
INPUT
INPUT
DATA
SET,
10%
50%
t su
50%
t R
t r
10%
50%
t PLH
90%
t WCPH
t hold
50%
90%
t TLH
t f
10
t WCPL
t su
t PHL
t hold
t THL
Family Specifications
MGK561
V DD
V SS
V DD
V SS
V OH
V OL
V DD