BUS-61571-xxxx Data Device, BUS-61571-xxxx Datasheet

BUS-61571-xxxx

Manufacturer Part Number

BUS-61571-xxxx

Description

MIL-STD-1553 Bc-rt-mt Integrated Terminal

Manufacturer

Data Device

Datasheet

1.BUS-61571-XXXX.pdf (4 pages)

Current page: 1 of 4
Download datasheet (50Kb)

DESCRIPTION

DDC’s BUS-61559 series of Advanced

Integrated Mux Hybrids with enhanced

RT Features (AIM-HY’er) comprise a

complete interface between a micro-

processor and a MIL-STD-1553B

Notice 2 bus, implementing Bus

Controller (BC), Remote Terminal (RX,

and Monitor Terminal (MT) modes.

Packaged in a single 78-pin DIP or

82-pin flat package the BUS-61559

series contains dual low-power trans-

ceivers and encoder/decoders, com-

plete BC/RT/MT protocol logic, memory

management and interrupt logic, 8K x 16

of shared static RAM, and a direct,

buffered interface to a host processor bus.

The BUS-61559 includes a number of

advanced features in support of

MIL-STD-1553B Notice 2 and STANAG

3838. Other salient features of the

BUS-61559 serve to provide the bene-

fits of reduced board space require-

ments enhanced software flexibility,

and reduced host processor overhead

The BUS-61559 contains internal

address latches and bidirectional data

WITH ENHANCED RT FEATURES (AIM-HY’er)

STROBE AND ERROR

(BROADCAST,

TIMING, DATA

INDICATORS)

MESSAGE

(ILLEGALIZATION

(RT ADDRESS)

(BROADCAST

RTFLAG)

(RTFAIL,

ENABLE)

ADVANCED INTEGRATED MUX HYBRIDS

ENABLE)

TX_INH_A

BUS-25679

buffers to provide a direct interface to

a host processor bus. Alternatively,

the buffers may be operated in a fully

transparent mode in order to interface

to up to 64K words of external shared

RAM and/or connect directly to a com-

ponent set supporting the 20 MHz

STANAG-3910 bus.

The memory management scheme

for RT mode prevails an option for

separation of broadcast data, in com-

pliance with 1553B Notice 2. A circu-

lar buffer option for RT message data

blocks offloads the host processor for

bulk data transfer applications.

Another feature besides those listed

to the right, is a transmitter inhibit con-

trol for the individual bus channels.

The BUS-61559 series hybrids oper-

ate over the full military temperature

range of -55 to +125”C and MIL-PRF-

38534 processing is available. The

hybrids are ideal for demanding mili-

tary and industrial microprocessor-to-

1553 applications

BCSTRCV, CMD_STR, TXDTA_STR

RXDTA_STR, MSG_ERR, INCMD

RTAD 4- , RTADP

ILLENA

RTFLAG

BRO_ENA

RTFAIL

TRANSCEIVER

LOW-POWER

BU-61559 BLOCK DIAGRAM

ILLEGALLIZATION

LOGIC

DUAL

ENCODER/

DECODER

BC/RT/MT

PROTOCOL

MIL-STD-1553B NOTICE 2

MEMORY ADDRESS

MANAGEMENT,

MEMORY DATA

PROCESSOR

INTERFACE,

INTERRUPT

MEMORY

SHARED

LOGIC

8K x 16

RAM/

DUAL

PORT

BUS-61559 SERIES

RAM

•

Notice 2 Interface Terminal

61553 AlM-HYSeries

Buffers for Dlrect Interface to

Processor Bus

to Support Bulk Data Transfers

RT Broadcast Data

Time Tag Registers

Illegalization

Available

TRANSPARENT/BUFFERED, MSTCLR,

Complete Integrated 1553B

Functlonal Superset of BUS-

Internal Address and Data

RT Subaddress Circular Buffers

Optlonal Separatlon of

Internal Interrupt Status and

Internal ST Command

MIL-PRF-38534 Processing

MEMEN-OUT,MEMWR, MEMOE

STRBD, SELECT, MEM/REG, RD/WR

IOEN, READYD

BUFFERS*

ADDRESS

LATCHES/

BUFFERS*

MEMENA-IN

DATA

SSFLAG

TAGCLK

INT

FEATURES

CLK IN (16MHz)

ADDR_LAT

D15-D

A15-A

(INTERRUPT

(SUBSYSTEM

REQUEST)

(PROCESSOR

CONTROL)

(MEMORY

(TIME TAG

CONTROL)

CLOCK)

FLAG)

(PROCESSOR

(ADDRESS

CONTROL)

ADDRESS)

LATCH

DATA)

Related parts for BUS-61571-xxxx

BUS-61571-xxxx Summary of contents

Page 1

... BC/RT/MT protocol logic, memory management and interrupt logic shared static RAM, and a direct, buffered interface to a host processor bus. The BUS-61559 includes a number of advanced features in support of MIL-STD-1553B Notice 2 and STANAG 3838. Other salient features of the ...

Page 2

... ORDERING INFORMATION BUS-615XX- XX0X* Supplemental Process Requirements Pre-Cap Source Inspection L = Pull Test Q = Pull Test and Pre-Cap Inspection K = One Lot Date Code W = One Lot Date Code and PreCap Source Y = One Lot Date Code and 100% Pull Test Z = One Lot Date Code, PreCap Source and 100% Pull Test ...

Page 3

NOTES 3 ...

Page 4

... The information in this data sheet is believed to be accurate; however, no responsibility is K-ABR assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. 105 Wilbur Place, Bohemia, New York 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7257 or 7381 Headquarters - Tel: (631) 567-5600 ext ...

Related keywords

BUS-61571-xxxx datasheet
BUS-61571-xxxx data sheet
BUS-61571-xxxx pdf datasheet
BUS-61571-xxxx component
BUS-61571-xxxx part
BUS-61571-xxxx distributor
BUS-61571-xxxx RoHS
BUS-61571-xxxx datasheet download