RM5261-200-QI PMC-Sierra Inc, RM5261-200-QI Datasheet - Page 33
RM5261-200-QI
Manufacturer Part Number
RM5261-200-QI
Description
RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released
Manufacturer
PMC-Sierra Inc
Datasheet
1.RM5261-200-QI.pdf
(40 pages)
- Current page: 33 of 40
- Download datasheet (684Kb)
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002241, Issue 1
9
9.1
9.2
AC Electrical Characteristics
Capacitive Load Deration
Clock Parameters
Parameter
Load Derate
IO Power Derate
IO Power Derate @ 20pF load
Parameter
SysClock High
SysClock Low
SysClock Frequency
SysClock Period
Clock Jitter for SysClock
SysClock Rise Time
SysClock Fall Time
ModeClock Period
JTAG Clock Period
Note
1.
Operation of the RM5261 is only guaranteed with the Phase Lock Loop Enabled.
1
Symbol
t
t
ModeCKP
JTAGCKP
t
t
t
SCH
SCP
t
t
SCL
t
CR
CF
JI
Symbol
C
LD
Test
Conditions
Transition
Transition
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Min
4.0
5ns
5ns
CPU Speed
200 MHz
Min
25
3
3
4
Max Min
100
256
40
200
2
2
Max
2
21
5.5
250 MHz
25
3
3
4
Max Min
125
256
40
150
2
2
Units
ns/25pF
mW/25pF/MHz
mW/MHz
266 MHz
33.3
3
3
4
Max
106
256
30
150
2
2
Released
Units
MHz
t
t
SCP
SCP
ns
ns
ns
ps
ns
ns
33
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