SC1153CSW.TR Semtech Corporation, SC1153CSW.TR Datasheet - Page 7

• Manufacturer Part Number: SC1153CSW.TR
• Description: PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS
• Manufacturer: Semtech Corporation

PRELIMINARY - October 3, 2000
OUTLINE DRAWING SO-20
THEORY OF OPERATION
The voltage at the VOSENSE pin is applied, through the internal precision resistor feedback chain, to the inverting
input of the error amplifier. The non-inverting input of the error amplifier is supplied with a DC voltage derived by
the DAC from the internal trimmed bandgap voltage reference. The output of the error amplifier is compared to the
triangular output of the internal oscillator to generate a fixed frequency, variable duty cycle pulse train. The internal
oscillator uses an on-chip capacitor and precision trimmed current sources to set the frequency to 200kHz.
The generated pulse train is gated with the output of the current limit latch and the inhibit signal to produce a drive
signal for the upper FET. It is also inverted to produce a drive signal for the lower FET. These FET drive signals
are modified by the “shoot-through control” circuitry so that the top FET turn-on is delayed until the bottom FET has
turned off, and visa-versa.
The current limit latch is set (ending the upper FET drive pulse early) if the current limit comparator indicates an
overcurrent condition. The latch is reset at the start of each oscillator period.
The PWRGOOD and OVP signals are derived from the voltage at the VOSENSE pin by comparators fed from the
internal feedback chain.
ECN00-1346
© 2000 SEMTECH CORP.
PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS
652 MITCHELL ROAD NEWBURY PARK CA 91320
Ref. MS-013AC
SC1153
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