SC16C2550 Philips Semiconductors, SC16C2550 Datasheet - Page 27

no-image

SC16C2550

Manufacturer Part Number
SC16C2550
Description
Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder
Manufacturer
Philips Semiconductors
Datasheets

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SC16C2550BIA44
Manufacturer:
EVERLIGHT
Quantity:
99
Part Number:
SC16C2550BIA44
Manufacturer:
NXP
Quantity:
3 224
Part Number:
SC16C2550BIA44
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
SC16C2550BIA44,512
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
SC16C2550BIA44,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
SC16C2550BIA44,529
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
SC16C2550BIA44518
Manufacturer:
NXP Semiconductors
Quantity:
135
Part Number:
SC16C2550BIB48
Manufacturer:
NXP
Quantity:
8 000
Part Number:
SC16C2550BIB48
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
SC16C2550BIB48128
Manufacturer:
NXP Semiconductors
Quantity:
1 889
Part Number:
SC16C2550BIB48151
Manufacturer:
NXP Semiconductors
Quantity:
135
Part Number:
SC16C2550BIBS,151
Manufacturer:
NXP
Quantity:
1 861
Part Number:
SC16C2550IN40
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Philips Semiconductors
9397 750 11621
Product data
7.10 Enhanced Feature Register (EFR)
7.9 Scratchpad Register (SPR)
Table 19:
[1]
The SC16C2550 provides a temporary data register to store 8 bits of user
information.
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
Table 20:
Bit
1
0
Bit
7
6
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
EFR[7]
EFR[6]
Modem Status Register bits description
Enhanced Feature Register bits description
Symbol
MSR[1]
MSR[0]
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
Description
Automatic CTS flow control.
Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will
be generated when the receive FIFO is filled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return to
a logic 0 when data is unloaded below the next lower trigger level
(programmed trigger level 1). The state of this register bit changes with the
status of the hardware flow control. RTS functions normally when
hardware flow control is disabled.
Rev. 03 — 19 June 2003
Logic 0 = Automatic CTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS flow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
0 = Automatic RTS flow control is disabled (normal default condition).
1 = Enable Automatic RTS flow control.
Description
DSR
CTS
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C2550 has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C2550 has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
[1]
[1]
…continued
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C2550
encoder/decoder
27 of 46

Related parts for SC16C2550