MX25L6402 Macronix International, MX25L6402 Datasheet - Page 7

• Manufacturer Part Number: MX25L6402
• Description: 64M-BIT [x 1] CMOS SERIAL eLite FlashTM MEMORY
• Manufacturer: Macronix International

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DATA SEQUENCE
Output data is serially sent out through SO pin, synchronized with the rising edge of SCLK, whereas input data is serially
read in through SI pin, synchronized with the rising edge of SCLK. The bit sequence for both input and output data is bit
7 (MSB) first, then bit 6, bit 5, ...., and bit 0.(LSB)
ADDRESS SEQUENCE
The address assignment is described as follows :
BA: Byte address Bit sequence:
AD1:First Address Bit sequence:
AD2:Second Address Bit sequence:
AD3:Thrid Address Bit sequence:
RESET OPERATION
The RESET pin provides a hardware method of resetting the device to reading array data. When the RESET pin is driven
low for at least a period of tRP, the device immediately terminates any operation in progress, tri-states all output pins, and
ignores all commands for the duration of the RESET pulse. The device also resets the internal state machine to reading
array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command
sequence, to ensure data integrity. Current is reduced for the duration of the RESET pulse. When RESET is held at VSS
+ 0.3V, the device draws reset current (ICC4). If RESET is held at VIL but not within VSS + 0.3V, the reset current will
be greater. The RESET pin may be tied to system reset circuitry. A system reset would that also reset the SPI memory.
Refer to the AC Characteristics tables for RESET parameters.
P/N: PM0943
X
X
A16
X
A6
X
A15 A14
X
A5
A22
X
A4
A21
A13
X
7
A3
A20
A12
X
A2
A19
A11
X
A1
A18
A10
A8
MX25L6402
A0
A17
A9
A7
REV. 1.0, SEP. 29, 2004