cy2dp818-2 Cypress Semiconductor Corporation., cy2dp818-2 Datasheet
cy2dp818-2
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cy2dp818-2 Summary of contents
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... Designed for data-communications clock-management appli- cations, the large fanout from a single input reduces loading on the input clock. The CY2DP818-2 is ideal for both level translations from single-ended to LVPECL and/or for the distribution of LVPECL-based clock signals. The Cypress CY2DP818-2 has configurable input functions. ...
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... Input Receiver Type Single-ended, non-inverting, inverting, void of bias resistors Low-voltage differential signaling Low-voltage pseudo (positive) emitter coupled logic LVTTL/LVCMOS Input Logic Input Logic Output Logic Q Pins, Q1A or Q1 Input Input Input Input CY2DP818-2 Description Min. Typ. Max. Unit 1.5 2.0 mA/ MHz 350 ...
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... Min – 3.3V ± 5 Conditions V = Min ohm Min ohm CY2DP818-2 Min. Max. Unit –0.3 4.6 –0 0.3 DD applied –0 0 –0 0.9 DD – –65 +150 ° °C – ...
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... User-defined by VTT RTT Max GND DD OUT = 3.3V ± 5 0°C to 70°C or –40°C to 85° Description Conditions 45%–55% duty cycle Standard load circuit Figure 1. Driver Design CY2DP818-2 = 0°C to 70°C or –40°C to 85°C) (continued) A Min. Typ. Max. Unit 300 1200 ps 2.1 – 3.0 V 0.8 – ...
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... V 0V Differential 1 PLH T PHL 80% 0V Differential QXA - QXB 20 150 GND 150 Standard Termination V I(A) 2.0V V 1.6V I(B) and t 1 ns; pulse rerate = 50 Mpps; pulse width = CY2DP818-2 TPA 50 TPC VDD-2V 50 TPB [2,3,4,5] TPA 50 TPC 50 TPB VOC VOD Next Device [2,3,4,5] 0.2 ns. – Page [+] Feedback ...
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... GND 150 Standard Termination 1.4V 1.0V 0. & Package Type 38-pin TSSOP 38-pin TSSOP–Tape and Reel 38-pin TSSOP 38-pin TSSOP–Tape and Reel CY2DP818-2 TPA 50 TPC VDD-2V 50 TPB 100% 80% 20 [2,3,4, fig [7] Figure 6 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY 38-lead TSSOP (4.40 mm Body) Z38 CY2DP818-2 51-85151-** Page [+] Feedback ...
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... Document History Page Document Title: CY2DP818-2 1:8 Clock Fanout Buffer Document Number: 38-07588 REV. ECN NO. Issue Date ** 129879 11/07/03 Document #: 38-07588 Rev. ** PRELIMINARY Orig. of Change Description of Change RGL New Data Sheet CY2DP818-2 Page [+] Feedback ...