cy28445-5 SpectraLinear Inc, cy28445-5 Datasheet - Page 17
![no-image](/images/no-image-200.jpg)
cy28445-5
Manufacturer Part Number
cy28445-5
Description
Clock Generator For Intel Calistoga Chipset
Manufacturer
SpectraLinear Inc
Datasheet
1.CY28445-5.pdf
(26 pages)
- Current page: 17 of 26
- Download datasheet (305Kb)
Rev 1.1, June 30, 2007
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (t
CPUC(Free Running
CPUT(Free Running
CPUC(Free Running)
CPUT(Free Running)
CPUC(Stoppable)
CPUT(Stoppable)
CPUC(Stoppable)
CPUT(Stoppable)
CPU_STOP#
CPU_STOP#
SRC 100MHz
DOT96C
DOT96T
DOT96T
DOT96C
PCI_STP#
PD
PCI_F
PD
PCI
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
Tsu
Figure 10. PCI STP# Assertion Waveform
SU
). (See
Figure 10.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free running.
CY28445-5
1.8 ms
1.8 ms
Page 17 of 26
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