mr25h40 Everspin Technologies, Inc, mr25h40 Datasheet - Page 2

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mr25h40

Manufacturer Part Number
mr25h40
Description
4mb Serial Spi Mram
Manufacturer
Everspin Technologies, Inc
Datasheet

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Everspin Technologies © 2011
1. DEVICE PIN ASSIGNMENT
Overview
The MR25H40 is a serial MRAM with memory array logically organized as 512Kx8 using the four pin inter-
face of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial peripheral inter-
face (SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM and Flash
components allowing MRAM to replace these components in the same socket and interoperate on a shared
SPI bus. Serial MRAM offers superior write speed, unlimited endurance, low standby & operating power, and
more reliable data retention compared to available serial memory alternatives.
System Configuration
Single or multiple devices can be connected to the bus as show in Figure 1.2. Pins SCK, SO and SI are com-
mon among devices. Each device requires CS and HOLD pins to be driven seperately.
HOLD
SCK
WP
CS
SI
Micro Controller
SPI
Figure 1.2 System Configuration
Instruction Register
Instruction Decode
Address Register
Clock Generator
Control Logic
Write Protect
Counter
Figure 1.1 Block Diagram
SCK
MOSI
MISO
CS
HOLD
CS
HOLD
1
2
1
2
EVERSPIN SPI MRAM 1
SO
CS
19
SI
2
HOLD
SCK
Document Number: MR25H40 Rev. 2, 1/2011
MRAM ARRAY
EVERSPIN SPI MRAM 2
CS
SO
Data I/O Register
MOSI = Master Out Slave In
MISO = Master In Slave Out
Nonvolatile Status
512Kb x 8
Register
SI
4
8
HOLD
SCK
MR25H40
SO

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