ds90cf582 National Semiconductor Corporation, ds90cf582 Datasheet

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... LVDS link Every cycle of the transmit clock 28 bits of input data are sampled and transmitted The DS90CF582 receiver converts the LVDS data streams back into 28 bits of CMOS TTL data At a transmit clock frequency of 40 MHz 24 bits of RGB data ...

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... Connection Diagrams DS90CF581 http www national com DS90CF582 TL F 12486 – 12486 – 4 ...

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... OUT 63W DS90CF582 1 61W above above 25 C Min Nom Max Units ) ...

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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter TRANSMITTER SUPPLY CURRENT I Transmitter Supply Current CCTW Worst Case I Transmitter Supply Current CCTG 16 Grayscale I Transmitter Supply Current CCTZ Power Down RECEIVER SUPPLY ...

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Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified (Continued) Symbol Parameter RCOH RxCLK OUT High Time (Figure 8) RxCLK OUT Low Time (Figure 8) RCOL RxOUT Setup to RxCLK OUT (Figure 8) RSRC RxOUT Hold to ...

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AC Timing Diagrams Note 1 The worst case test pattern produces a maximum toggling of digital circuits LVDS I O and CMOS TTL I O Note 2 The 16 grayscale test pattern tests device power consumption for a ‘‘typical’’ LCD ...

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... TL F 12486 – 8 FIGURE 3 DS90CF581 (Transmitter) LVDS Output Load and Transition Timing TL F 12486 – 10 FIGURE 4 DS90CF582 (Receiver) CMOS TTL Output Load and Transition Timing FIGURE 5 DS90CF581 (Transmitter) Input Clock Transition Time FIGURE 6 DS90CF581 (Transmitter) Channel-to-Channel Skew and Pulse Width ...

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... FIGURE 7 DS90CF581 (Transmitter) Setup Hold and High Low Times FIGURE 8 DS90CF582 (Receiver) Setup Hold and High Low Times FIGURE 9 DS90CF581 (Transmitter) Clock In to Clock Out Delay FIGURE 10 DS90CF582 (Receiver) Clock In to Clock Out Delay http www national com TL F 12486 – 12486 – ...

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... AC Timing Diagrams (Continued) FIGURE 11 DS90CF581 (Transmitter) Phase Lock Loop Set Time FIGURE 12 DS90CF582 (Receiver) Phase Lock Loop Set Time 12486 – 12486 – 21 http www national com ...

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AC Timing Diagrams (Continued) FIGURE 13 Seven Bits of LVDS in One Block Cycle FIGURE 14 28 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF581) http www national com 12486 – 12486 – ...

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... PLL GND I 2 Ground pins for PLL LVDS Power supply pin for LVDS outputs CC LVDS GND I 3 Ground pins for LVDS outputs DS90CF582 Pin Description FPD Link Receiver Pin Name RxIN I 4 Positive LVDS differential data inputs b RxIN I 4 ...

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... Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package JEDEC Order Number DS90CF581MTD or DS90CF582MTD LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL ...