upd16670 Renesas Electronics Corporation., upd16670 Datasheet
upd16670
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upd16670 Summary of contents
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DUTY LCD CONTROLLER/DRIVER DESCRIPTION The PD16670 is a LCD controller/driver with 1/17, 1/25 and 1/33 duty capable of displaying a dot matrix LCD. It has 60 segment outputs, 33 common outputs, giving a maximum display capability of ...
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BLOCK DIAGRAM SEG 1 Segment Driver 60 bit Shift Register Parallel/Serial Conversion Circuit 5 CGRAM/ Pictograph RAM bit 5 STB SCK Serial I/F DATA TDATA /RESET /LCDOFF TEST Remark /xxx indicates active low signals. ...
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PIN CONFIGURATION (Pad Layout) 2 Chip size: 4. 116 Data Sheet S10297EJ1V0DS00 PD16670 ...
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PAD No. Pad Name LCD 9 V LC1 10 V LC2 11 V LC3 ...
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PIN FUNCTIONS Pin Symbol Pin Name SEG to SEG Segment 1 60 COM to COM Common 1 33 SCK Shift clock DATA Data STB Strobe /LCDOFF LCD off input /RESET Reset TDATA Test output TEST Test pin 17 OSC ...
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Figure 3 1. Example of LCD driver’s circuit and external circuit for boosted circuit LCD LC1 + LC2 + LC3 + ...
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LCD DISPLAY DRIVER PD16670 segment display and pictograph display segments can be driven. (1) Example of 1/17 duty connection: 12 columns x 2 lines + 60 pictograph displays 2 4 SEG ...
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Example of 1/25 duty connection: 12 columns x 3 lines + 60 pictograph displays 2 4 SEG COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 ...
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Example of 1/33 duty connection: 12 columns x 4 lines + 60 pictograph displays 2 4 SEG COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 ...
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CHARACTER CODE The relation between character codes and character patterns is shown below. Character codes [0xxx] are allocated to CGRAM. Higher bits 0000 0001 0010 Lower 4 bits bits 4 bits CG RAM XXXX0000 (1) (2) XXXX0001 (3) XXXX0010 ...
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DESCRIPTION OF BLOCKS 6.1 Display Data RAM (DDRAM) DDRAM addresses are allocated as shown below 1st line 00H 01H 02H 2nd line 12H 13H 14H 3rd line 24H 25H 26H 4th line 36H 37H 38H Caution ...
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Character Generator RAM (CGRAM) CGRAM is RAM to which the user can freely set character patterns. Eight types dot character patterns can be defined. CGRAM is the RAM that contains pictograph display data. The relation ...
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Pictograph Display RAM (PDRAM) Pictograph display RAM addresses used to some parts of CGRAM is shown below. CGRAM address 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH ...
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COMMANDS 7.1 Basic format Command register (CR) Address register (AR) 7.2 Command register The command register’s basic configuration is as follows. MSB 7.2.1 Reset This command resets all of the commands ...
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Standby This command stops the DC/DC converter, which reduces the supply current. The display is set to OFF mode (SEG , COM = LC5 LSB MSB 7.2.4 ...
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Address Register This command selects the address type and specifies addresses. MSB Caution Operation is not guaranteed if an invalid address is set. 7.4 Reset The contents of the various registers appear ...
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CPU ACCESS EXAMPLES Examples of access procedure are shown below. 8.1 Initialize and Data Write Parameter STB b7 Start H X Reset Duty setting Address register Address register ...
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Initialize and Data Write (unused pictograph) Parameter STB b7 Start H X Reset Duty setting Address register Address register CGRAM data1 ...
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Change display data Parameter STB b7 Start H X Address register Address register Character data Character data Character data Character data ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Logic power supply voltage Logic input voltage Driver supply voltage Driver reference supply input voltage Logic system output voltage (SEG , COM ) n n Operating ambient ...
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Electrical characteristics (Unless otherwise specified, T Parameter Symbol High-level input voltage 1 V IH1 Low-level input voltage 1 V IL1 High-level input voltage 2 V IH2 Low-level input voltage 2 V IL2 High-level input current I IH Low-level input current ...
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Switching characteristics (Unless otherwise specified, T Parameter Symbol Oscillation frequency f OSC Required timing conditions (Unless otherwise specified, T Parameter Symbol Clock frequency f OSC High-level clock pulse width t WHC Low-level clock pulse width t WLC Shift clock cycle ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Semiconductor Device Mounting Technology (C10535E) The information in this document is current as of September, 2000. The information is subject to change without notice. For actual design-in, refer to the latest ...