upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 309
upd78f0103hmca1-5a4-a
Manufacturer Part Number
upd78f0103hmca1-5a4-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD78F0103HMCA1-5A4-A.pdf
(438 pages)
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17.1 Functions of Clock Monitor
reset signal when the high-speed system clock is stopped.
to 1. For details of RESF, see CHAPTER 16 RESET FUNCTION.
17.2 Configuration of Clock Monitor
Control register
The clock monitor samples the high-speed system clock using the internal oscillator, and generates an internal
When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set
The clock monitor automatically stops under the following conditions.
• Reset is released and during the oscillation stabilization time
• In STOP mode and during the oscillation stabilization time
• When the high-speed system clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation
• When the internal oscillation clock is stopped
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
The clock monitor includes the following hardware.
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
stabilization time
Item
High-speed system clock oscillation
High-speed system clock oscillation
stabilization status (OSTC overflow)
OSTC:
control signal (MSTOP)
Clock monitor mode register (CLM)
Oscillation stabilization time counter status register (OSTC)
Figure 17-1. Block Diagram of Clock Monitor
Table 17-1. Configuration of Clock Monitor
CHAPTER 17 CLOCK MONITOR
High-speed system clock
Internal oscillation clock
User’s Manual U16846EJ3V0UD
Operation mode
Internal bus
controller
CLME
Clock monitor
mode register (CLM)
Configuration
High-speed system
clock oscillation
monitor circuit
Internal reset
signal
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