si3200-x-gs Silicon Laboratories, si3200-x-gs Datasheet - Page 84
si3200-x-gs
Manufacturer Part Number
si3200-x-gs
Description
Dual Programmable Cmos Slic With Line Monitoring
Manufacturer
Silicon Laboratories
Datasheet
1.SI3200-X-GS.pdf
(128 pages)
- Current page: 84 of 128
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Si3232
RINGCON: Ringing Configuration (Register Address 23)
(Register type: Initialization)
Reset settings = 0x00
84
Name ENSYNC RDACEN RINGUNB
Type
Bit
Bit
7
6
5
4
3
2
1
0
UNBPOLR
RINGUNB
RDACEN
ENSYNC
RINGEN
Name
TAEN
TRAP
D7
TIEN
R
D6
R
Ringing Waveform Present Flag.
0 = No ringing waveform present.
1 = Ringing waveform present.
Ringing Waveform Sent to Differential DAC.
0 = Ringing waveform not sent to differential DAC.
1 = Ringing waveform set to differential DAC.
Unbalanced Ringing Enable.
Enables internal unbalanced ringing generation.
0 = Unbalanced ringing not enabled.
1 = Unbalanced ringing enabled.
Ringing Active Timer Enable.
0 = Ringing active timer disabled.
1 = Ringing active timer enabled.
Ringing Inactive Timer Enable.
0 = Ringing inactive timer disabled.
1 = Ringing inactive timer enabled.
Ringing Oscillator Enable Monitor.
This bit will toggle when the ringing oscillator is enabled and disabled.
0 = Ringing oscillator is disabled.
1 = Ringing oscillator is enabled.
Reverse Polarity Unbalanced Ringing Select. The RINGOF RAM location must be
modified from its normal ringing polarity setting. Refer to “4.7. Internal Unbalanced
Ringing” for details.
0 = Normal polarity ringing.
1 = Reverse polarity ringing.
Ringing Waveform Selection.
0 = Sinusoid waveform.
1 = Trapezoid waveform.
R/W
D5
Preliminary Rev. 0.96
TAEN
R/W
D4
TIEN
R/W
D3
Function
RINGEN
D2
R
UNBPOLR
R/W
D1
TRAP
R/W
D0
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