74HCT174D,652 NXP Semiconductors, 74HCT174D,652 Datasheet - Page 2
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74HCT174D,652
Manufacturer Part Number
74HCT174D,652
Description
IC HEX D F-F POS-EDGE 16-SOIC
Manufacturer
NXP Semiconductors
Series
74HCTr
Type
D-Type Busr
Datasheets
1.74HCT4046ADB112.pdf
(19 pages)
2.74HCT4046ADB112.pdf
(23 pages)
3.74HCT174N652.pdf
(13 pages)
Specifications of 74HCT174D,652
Output Type
Inverted
Package / Case
16-SOIC (3.9mm Width)
Function
Master Reset
Number Of Elements
1
Number Of Bits Per Element
6
Frequency - Clock
63MHz
Delay Time - Propagation
21ns
Trigger Type
Positive Edge
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
1
Logic Family
HCT
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
18 ns
High Level Output Current
- 4 mA
Low Level Output Current
4 mA
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
4.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-2796-5
933715050652
933715050652
Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT174 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
1998 Jul 08
SYMBOL
t
f
C
C
PHL
max
Six edge-triggered D-type flip-flops
Asynchronous master reset
Output capability: standard
I
I
PD
Hex D-type flip-flop with reset; positive-edge trigger
CC
f
f
C
V
For HCT the condition is V
i
o
/ t
CC
PD
= input frequency in MHz
L
category: MSI
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
2
= 25 C; t
V
f
o
PARAMETER
propagation delay
maximum clock frequency
input capacitance
power dissipation
CC
capacitance per flip-flop
) = sum of outputs
CP to Q
MR to Q
2
r
f
i
= t
+ (C
f
I
I
n
n
= 6 ns
= GND to V
= GND to V
L
V
CC
2
CC
CC
f
o
) where:
1.5 V
2
The 74HC/HCT174 have six edge-triggered D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time prior to the LOW-to-HIGH clock
transition, is transferred to the corresponding output of the
flip-flop.
A LOW level on the MR input forces all outputs LOW,
independently of clock or data inputs.
The device is useful for applications requiring true outputs
only and clock and master reset inputs that are common to
all storage elements.
CONDITIONS
notes 1 and 2
C
D
L
= 15 pF; V
in W):
CC
= 5 V
HC
17
13
99
3.5
17
TYPICAL
74HC/HCT174
Product specification
HCT
18
17
69
3.5
17
UNIT
ns
ns
MHz
pF
pF