si4330 Silicon Laboratories, si4330 Datasheet - Page 119
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si4330
Manufacturer Part Number
si4330
Description
Si4330 Ism Receiver
Manufacturer
Silicon Laboratories
Datasheet
1.SI4330.pdf
(142 pages)
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Register 56h. Modem Test
Reset value = 00000000
Name
Type
Bit
Bit
7
6
5
4
3
2
1
0
bcrfbyp
oscdeten
refclksel
refclkinv
bcrfbyp
slicfbyp
distogg
R/W
Name
dttype
D7
ookth
slicfbyp
If set, BCR phase compensation will be bypassed.
If set, slicer phase compensation will be bypassed.
Dithering Type.
If low and dither enabled, we add +1/0, otherwise if high and dithering enabled, we add
±1.
If low, the ADC Oscillation Detection mechanism is allowed to work. If set, we disable the
function.
If set, in OOK mode, the slicer threshold will be estimated by 8 bits of preamble. By
default, this bit is low and the demod estimate the threshold after 4 bits.
Delta-Sigma Reference Clock Source Selection
1:
0:
Delta-Sigma Reference Clock Inversion Enable.
If reset, the discriminator toggling is disabled.
R/W
D6
10 MHz
PLL
dttype
R/W
D5
Preliminary Rev 0.2
oscdeten
R/W
D4
Function
ookth
R/W
D3
refclksel
R/W
D2
refclkinv
R/W
D1
Si4330
distogg
R/W
D0
119