si4330 Silicon Laboratories, si4330 Datasheet - Page 120
![no-image](/images/no-image-200.jpg)
si4330
Manufacturer Part Number
si4330
Description
Si4330 Ism Receiver
Manufacturer
Silicon Laboratories
Datasheet
1.SI4330.pdf
(142 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
si4330-A0-FM
Manufacturer:
SILICON
Quantity:
740
Part Number:
si4330-A0-FM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
si4330-B1-FM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
si4330-B1-FM-02T
Manufacturer:
SILICON
Quantity:
112
Company:
Part Number:
si4330-B1-FMR
Manufacturer:
HIROSE
Quantity:
3 200
Part Number:
si4330-B1-FMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
si4330BDY-T1-E3
Manufacturer:
VISHAY/威世
Quantity:
20 000
Part Number:
si4330BDY-T1-GE3
Manufacturer:
VISHAY/威世
Quantity:
20 000
Company:
Part Number:
si4330DY-T1-E3
Manufacturer:
VISHAY
Quantity:
464
Company:
Part Number:
si4330DY-T1-E3
Manufacturer:
VISHAY
Quantity:
30 000
Register 57h. Charge Pump Test
Register 58h. Charge Pump Current Trimming/Override
Si4330
Reset value = 00000000
Reset value = 100xxxxx
120
Name
Name
Type
Type
Bit
Bit
2:0
7:6
4:0
Bit
Bit
7
6
5
4
3
5
cdcurr[2:0]
cpcurr[1:0]
cpcorr[4:0]
cpforceup
cpforcedn
fbdiv_rst
cpcorrov
pfdrst
cdconly
R/W
Name
Name
D7
pfdrst
D7
cpcurr[1:0]
R/W
fbdiv_rst
Direct Control to Analog.
Direct Control to Analog.
Charge Pump Force Up.
Charge Pump Force Down.
Charge Pump DC Offset Only.
Charge Pump DC Current Selection.
Charge Pump Current (Gain Setting).
Changing these bits will change the BW of the PLL. The default setting is adequate for all
data rates.
Charge Pump Correction Override Enable.
Charge Pump Correction Value.
During read, you read what the Charge Pump sees. If cpcorrov = 1, then the value you
write will go to the Charge Pump, and will also be the value you read. By default,
cpcorr[4:0] wakes up as all Zeros.
R/W
D6
D6
cpforceup
cpcorrov
R/W
R/W
D5
D5
Preliminary Rev 0.2
cpforcedn
R/W
D4
D4
Function
Function
cdonly
R/W
D3
D3
cporr[4:0]
R/W
D2
D2
cdcurr[2:0]
R/W
D1
D1
D0
D0