st7033 Sitronix Technology Corporation, st7033 Datasheet
st7033
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st7033 Summary of contents
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... Sitronix 1. INTRODUCTION The ST7033 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 96 segment and 4 common driver circuits. This chip is connected directly to a microprocessor, accepts 3-line serial peripheral interface (SPI), display data can stores in an on-chip display data RAM bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption ...
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... ST7033 3. ST7033 PAD ARRANGEMENT (COG) Dice Size: 5080um X 770um Bump Height: 15um Chip Thickness: 300um Bump Pitch: PAD Number 1~23, 120~142, 143~153, 227~238: 24~119: 154~199, 213~226: 200~205, 207~212: 23-24: 119-120: Ver 1.0 Pitch (um) PAD Number 37.2 153-154: 33 199-200 59.3 205-206, 206-207 33.3 212-213 69.1 226-227 60.70 2/39 Pitch (um) 86.97 46.66 38.8 53.44 79.9 2008/05/29 ...
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... ST7033 4-1. PAD CENTER COORDINATES NO. NAME 2450. 2413. 2376. 2339. 2302. 2264. 2227. 2190. 2153. 2116. 2078. 2041. 2004. 1967. 1930. 1892. 1855. 1818.40 ...
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... ST7033 NO. NAME X 91 SEG[67] -647.71 92 SEG[68] -680.71 93 SEG[69] -713.71 94 SEG[70] -746.71 95 SEG[71] -779.71 96 SEG[72] -812.71 97 SEG[73] -845.71 98 SEG[74] -878.71 99 SEG[75] -911.71 100 SEG[76] -944.71 101 SEG[77] -977.71 102 SEG[78] -1010.71 103 SEG[79] -1043.71 104 SEG[80] -1076.71 105 SEG[81] -1109.71 106 SEG[82] -1142 ...
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... ST7033 NO. NAME X 187 D[2] -34.78 188 D[1] 24.54 189 D[0] 83.84 190 OSC 143.15 191 VDD1 202.45 192 VDD1 261.75 193 VDD1 321.06 194 VDD1 380.37 195 VDD2 439.67 196 VDD2 498.97 197 VDD2 558.28 198 VDD2 617.59 199 VRS 676.89 200 T[1] 723.54 201 T[2] 756.84 202 T[3] 790.14 ...
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... ST7033 5. BLOCK DIAGRAM Ver 1.0 Figure 1. Block Diagram 6/39 2008/05/29 ...
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... ST7033 6. PINNING DESCRIPTIONS Pin Name I/O LCD driver outputs LCD segment driver outputs. The display data and the M signal control the output voltage of segment driver. SEG0 to SEG95 O LCD column driver outputs. The internal scanning data and the M signal control the output voltage of common driver ...
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... ST7033 Read/Write operation control pin (if using Parallel interface). E_RD I Data Bus. If /CSB signal is not actived, D7…D0 are high impedance. D0…D7 I LCD DRIVER SUPPLY OSC I POWER SUPPLY VSS Power Ground. Digital circuits supply voltage. VDD1 Power The 2 power supply rails, VDD1 and VDD2, could be connected together. ...
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... ST7033 Test pin Must fix to “L” Test Pin T0~T12 --- Test pins. Do not use these pins. Mirror X: SEG bi-direction selection (refer to pad center coordinates). TMX I TMX connect to VSS :MX mode1(refer to segment driver direction select) TMX connect to VDD1 :MX mode2(refer to segment driver direction select) Mirror Y: COM bi-direction selection (refer to pad center coordinates) ...
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... FUNCTIONS DESCRIPTION MICROPROCESSOR INTERFACE Chip Select Input There is /CSB pin for chip selection. The ST7033 can interface with an MPU when /CSB is "L". When /CSB is “H”, the internal shift register and the counter are reset. Parallel / Serial Interface ST7033 has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial interface is determined by PS [1:0] pin as shown in Table 1 ...
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... PS1= “L”, PS0= “H”: 4-line SPI interface When the ST7033 is active (/CSB=”L”), serial data (D1) and serial clock (D0) inputs are enabled. When /CSB is “High”, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication is controlled by the register selection pin (A0) ...
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... This allows the MPU display data to be accessed continuously. ADDRESSING Data is downloaded in bytes into the RAM matrix of ST7033 as indicated in Figure 4. The display RAM has a matrix bits. The address pointer addresses the columns. The column address ranges are (1011111), .Addresses outside these ranges are not allowed ...
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... ST7033 Data Structure Data Column Address Start Normal direction MX=0 SEG output Reverse direction MX=1 Ver 1.0 …… D4~D7 are disabled bits …… …… …… Figure 4. Display Data RAM Map (1/4 Duty) 13/39 Line COM output Address Start 00H ...
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... COM0 Method 4 COM1 SEGn+1 DP Figure 5. Relationships between LCD layout and display RAM filling order and display data Notes 1 ： ’ x ‘= data bit unchanged. Notes 2 ： ST7033 is always operating in 1/4 duty. Ver 1.0 LCD COM SEGn SEGn+1 COM0 c b COM1 ...
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... ST7033 LCD DRIVER CIRCUIT 4-channel common drivers and 96-channel segment drivers configure this driver circuit. This LCD panel driver voltage depends on the combination of display data and frame (positive or negative). Liquid Crystal Driver Power Circuit The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components ...
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... ST7033 8. RESET CIRCUIT Setting /RESB to “L” or Reset instruction can initialize internal function. When /RESB becomes “L”, following procedure is occurred. Power save mode is entered --Oscillator circuit is stopped --The LCD power supply circuit is stopped --Display OFF --Display all point ON --Segment/Common output go to the VSS level ...
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... ST7033 9-1. INSTRUCTION TABLE COMMAND A0 D7 Display data write 1 D7 Display ON/OFF 0 1 Display 0 1 normal/reverse Display all points 0 1 ON/OFF Page address set 0 1 Column address set 0 0 Upper 3-bit address Column address set 0 0 Lower 4-bit address Segment driver 0 1 direction select ...
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... ST7033 9-2. INSTRUCTION DESCRIPTION Display data Write 8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address . The column address is increased by 1 automatically so that the microprocessor can continuously write data . During auto-increment, the column address wraps to 0 after the last column is written. ...
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... ST7033 Segment Driver Direction Select This command can reverse the correspondence between the DDRAM column address and the segment driver output ...
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... ST7033 Power Save Mode If the display all points ON command is executed when the display is in display OFF mode, power saver mode is entered. This mode stops every operation of the LCD display system. Power save (Display OFF & Display all points ON) Power save OFF (Display all points OFF) ...
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... ST7033 Command Description Referential instruction setup flow for power on: Referential instruction setup flow for power down: Ver 1.0 Figure 9. Power On and Power Down Sequence 21/39 2008/05/29 ...
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... ST7033 10. LIMITING VALUES In accordance with the Absolute Maximum Rating System; see notes 1 and 2. Parameter Power supply voltage Power supply voltage Power supply voltage (VDD2 standard) Power supply voltage (VDD2 standard) Operating temperature Storage temperature Notes 1. Stresses above those listed under Limiting Values may cause permanent damage to the device. ...
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... ST7033 11. HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However totally safe desirable to take normal precautions appropriate to handling MOS devices 12. DC CHARACTERISTICS Item Symbol Operating Voltage (1) Operating Voltage (2) High-level Input Voltage Low-level Input Voltage High-level Output Voltage ...
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... ST7033 Dynamic Consumption Current : During Display, with the Internal Power Supply ON Current consumed by total ICs(bare die) Test pattern Symbol Power Down ISS Notes to the DC characteristics 1. The maximum possible V0 oltage that may be generated is dependent on voltage, temperature and (display) load. 2. During power down all static currents are switched off. ...
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... ST7033 13. TIMING CHARACTERISTICS System Bus Read/Write Characteristics 1 (For the 8080 Series MPU AW8 /CSB WR, (Write (Read) Figure 11. Parallel 8080 Series Interface Characteristics Item Address hold time Address setup time Address setup time System cycle time Enable L pulse width (WRITE) ...
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... ST7033 Item Address hold time Address setup time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) WRITE Data setup time WRITE Address hold time Item Address hold time Address setup time Address setup time System cycle time ...
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... ST7033 System Bus Read/Write Characteristics 1 (For the 6800 Series MPU) A0 R/W t AW6 /CSB (Write (Read) Figure 12. Parallel 6800 Series Interface Characteristics Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) ...
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... ST7033 Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) WRITE Data setup time WRITE Address hold time Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) ...
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... ST7033 SERIAL INTERFACE (4-Line Interface) /CSB A0 SCLK SDA Item Serial Clock Period SCL “H” pulse width SCL “L” pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time Item Serial Clock Period SCL “ ...
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... ST7033 Item Serial Clock Period SCL “H” pulse width SCL “L” pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time Notes1: The input signal rise and fall time (tr, tf) are specified less. ...
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... ST7033 SERIAL INTERFACE (3-Line Interface) Item Serial Clock Period(Write) SCL “H” pulse width(Write) SCL “L” pulse width(Write) Data setup time Data hold time CS-SCL time CS-SCL time SCL-CS CS “H” pulse width Ver 1.0 Figure 14. 3- Line Serial Interface Characteristics ...
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... ST7033 Item Serial Clock Period(Write) SCL “H” pulse width(Write) SCL “L” pulse width(Write) Data setup time Data hold time CS-SCL time CS-SCL time SCL-CS CS “H” pulse width Item Serial Clock Period(Write) SCL “H” pulse width(Write) SCL “L” pulse width(Write) ...
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... ST7033 14. RESET TIMING t RJ /RESB Internal status Item Reset time Reset “L” pulse width Reset rejection (for noise spike) /RESB tRJ Item Reset time Reset “L” pulse width Reset rejection (for noise spike) /RESB tRJ Item Reset time Reset “L” pulse width Reset rejection (for noise spike) /RESB tRJ Ver 1 ...
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... ST7033 15. APPLICATION NOTE ............................................. ................ IC PAD SIDE Ver 1.0 ............................................. ............................................. ST7033 C=1.0uF R=1M ohm C=0.1uF Figure 16. 6800 Parallel Application 34/39 .......................................... ......... 2008/05/29 ...
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... ST7033 ............................................. ................ IC PAD SIDE Ver 1.0 ............................................. ............................................. ST7033 C=1.0uF R=1M ohm C=0.1uF Figure 17. 8080 Parallel Applicaiton 35/39 .......................................... ......... 2008/05/29 ...
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... ST7033 Ver 1.0 Figure 18. 3-Line Serial Application 36/39 2008/05/29 ...
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... ST7033 ............................................. ................ IC PAD SIDE Ver 1.0 ............................................. ............................................. ST7033 C=1.0uF R=1M ohm C=0.1uF Figure 19. 4-Line Serial Application 37/39 .......................................... ......... 2008/05/29 ...
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... ST7033 ITO Layout Reference About ITO layout, please refer the following pictures ： Ver 1.0 38/39 2008/05/29 ...
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... ST7033 Version Date 1.0 2008/04/18 First Issue Version Ver 1.0 ST7033 Serial Specification Revision History Description 39/39 2008/05/29 ...