sm55161a-80hkcm Austin Semiconductor, Inc., sm55161a-80hkcm Datasheet - Page 14
sm55161a-80hkcm
Manufacturer Part Number
sm55161a-80hkcm
Description
262144 X 16 Bit Vram Multiport Video Ram
Manufacturer
Austin Semiconductor, Inc.
Datasheet
1.SM55161A-80HKCM.pdf
(64 pages)
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FIGURE 8: Example of a Persistent Write-Per-Bit Operation
persistent write-per-bit
performing a load-write-mask-register (LMR) cycle. In the
persistent write-per-bit mode, the write-per-bit mask is
overwritten but remains valid over an arbitrary number of write
cycles until another LMR cycle is performed or power is
removed.
timing with DSF held high on the falling edge of RAS\ and held
low on the first falling edge of CASx\. A binary code is input to
SMJ55161A
Rev. 1.6 03/05
The persistent write-per-bit mode is initiated by
The LMR cycle is performed using DRAM write-cycle
Austin Semiconductor, Inc.
14
the write-mask register via the random I/O pins and latched on
either the first falling edge of CASx\ or the falling edge of WE\,
whichever occurs later. Byte write control can be applied to the
write mask during the LMR cycle. The persistent write-per-bit
mode can then be used in exactly the same way as the
nonpersistent write-per-bit mode except that the input data on
the falling edge of RAS\ is ignored. When the device is set to
the persistent write-per-bit mode, it remains in this mode and is
reset only by a CBR refresh (option-reset) cycle (see Figure 8).
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Production
SM55161A
VRAM
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