ds3171n Maxim Integrated Products, Inc., ds3171n Datasheet - Page 30
ds3171n
Manufacturer Part Number
ds3171n
Description
Ds3171, Ds3172, Ds3173, Ds3174 Single/dual/triple/quad Ds3/e3 Single-chip Transceivers
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS3171N.pdf
(234 pages)
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PIN NAME
TOHSOFn
ROHCLKn
ROHSOFn
TOHCLKn
TOHENn
ROHn
TOHn
TYPE
O
O
O
O
O
I
I
Transmit Overhead
TOHn: When the port framer is configured for one of the DS3 or E3 framing modes, this signal
will be used to over-write the DS3 or E3 framing overhead bits when TOHENn is active. In T3
mode, the X-bits, P-bits, M-bits, F-bits, and C-bits are input. In G.751 E3 mode, all of the FAS,
RAI, and National Use bits are input. In G.832 E3 mode, all of the FA1, FA2, EM, TR, MA, NR,
and GC bytes are input. The TOHSOFn signal marks the start of the framing bit sequence. This
signal is sampled at the same time as the TOHCLKn signal transitions high to low.
This signal can be inverted.
Transmit Overhead Enable / Start Of Frame Input
TOHENn: When the port framer is configured for one of the DS3 or E3 framing modes, this
signal will be used the determine which DS3 or E3 framing overhead bits to over-write with the
signal on the TOHn pins. The TOHSOFn signal marks the start of the framing bit sequence.
This signal is sampled at the same time as the TOHCLKn signal transitions high to low.
This signal can be inverted.
Transmit Overhead Clock
TOHCLKn: When the port framer is configured for one of the DS3 or E3 framing modes, this
clock is used for the transmit overhead port signals TOHn, TOHENn and TOHSOFn. The
TOHSOFn output signal is updated and the TOHn and TOHENn input signals are sampled at
the same time this clock signal transitions from high to low. The external logic is expected to
sample TOHSOFn signal and update the TOHn and TOHENn signals on the rising edge of this
clock signal. This clock is a low frequency clock.
This signal can be inverted.
Transmit Overhead Start Of Frame
TOHSOFn: When the port framer is configured for one of the DS3 or E3 framing modes, this
signal is used to mark the start of a DS3 or E3 overhead sequence on the TOHn pins. In T3
mode, the first X-bit is marked. In G.751 E3 mode, the first bit of the FAS word is marked. In
G.832 E3 mode, the first bit of the FA1 byte is marked. The sequence starts on the same high
to low transition of the TOHCLKn clock that this signal is high. This signal is updated at the
same time as the TOHCLKn signal transitions high to low.
This signal can be inverted.
Receive Overhead
ROHn: When the port framer is configured for one of the DS3 or E3 framing modes, this signal
outputs the value of the receive overhead bits. The ROHSOFn signal marks the start of the
framing bit sequence. In T3 mode, the X-bits, P-bits, M-bits, F-bits, and C-bits are output (Note:
In M23 mode, the C-bits are extracted even though they are marked as data at the payload
interface). In G.751 E3 mode, all of the FAS, RAI, and National Use bits are output. In G.832
E3 mode, all of the FA1, FA2, EM, TR, MA, NR, and GC bytes are output.
This signal is updated at the same time as the ROHCLKn signal transitions high to low.
This signal can be inverted.
Receive Overhead Clock
ROHCLKn: When the port framer is configured for one of the DS3 or E3 framing modes, this
clock is used for the receive overhead port signals ROHn and ROHSOFn. The ROHSOFn and
ROHn output signals are updated at the same time this clock signal transitions from high to low.
The external logic is expected to sample ROHSOFn and ROHn signal on the rising edge of this
clock signal. This clock is a low frequency clock.
This signal can be inverted.
Receive Overhead Start Of Frame
ROHSOFn: When the port framer is configured for one of the DS3 or E3 framing modes this
signal is used to mark the start of a DS3 or E3 overhead sequence on the ROHn pins. In T3
mode, the first X-bit is marked. In G.751 E3 mode, the first bit of the FAS word is marked. In
G.832 E3 mode, the first bit of the FA1 byte is marked. The sequence starts on the same high
to low transition of the ROHCLKn clock that this signal is high. This signal is updated at the
same time as the ROHCLKn signal transitions high to low.
This signal can be inverted.
DS3/E3 OVERHEAD INTERFACE
30
PIN DESCRIPTION
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