t6020m ATMEL Corporation, t6020m Datasheet - Page 11

• Manufacturer Part Number: t6020m
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

Table 2 Interrupt priority table
Table 3 Hardware interrupts
The programmer can generate interrupts by using the
software interrupt instruction (SWI) which is supported
in qFORTH by predefined macros named SWI0...SWI7.
The software triggered interrupt operates exactly like any
hardware triggered interrupt. The SWI instruction takes
the top two elements from the expression stack and writes
the corresponding bits via the I/O bus to the interrupt
pending register. Therefore, by using the SWI instruction,
interrupts can be re-prioritized or lower priority processes
scheduled for later execution.
In the T6020M, there are eleven hardware interrupt
sources with seven different levels. Each source can be
masked individually by mask bits in the corresponding
control registers. An overview of the possible hardware
configurations is shown in table 4.
Rev. A3, 02-Apr-01
Interrupt
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
Interrupt
INT1
INT2
INT3
INT4
INT6
INT7
Software Interrupts
Hardware Interrupts
Priority
highest
lowest
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Register
T2CM
P5CR
P5CR
VCM
T1M
SISC
ROM Address
0C0h
1C0h
1E0h
040h
080h
100h
140h
180h
Interrupt Mask
P52M1, P52M2
P53M1, P53M2
P50M1, P50M2
P51M1, P51M2
C8h (SCALL 040h)
D0h (SCALL 080h)
D8h (SCALL 0C0h)
E8h (SCALL 100h)
E8h (SCALL 140h)
F0h (SCALL 180h)
F8h (SCALL 1C0h)
FCh (SCALL 1E0h)
T1IM
T2IM
VIM
SIM
Bit
Interrupt Opcode
2.3
The master reset forces the CPU into a well-defined
condition. It is unmaskable and is activated independent
of the current program state. It can be triggered by either
initial supply power-up, a short collapse of the power sup-
ply, brown-out detection circuitry, watchdog time-out, or
an external input clock supervisor stage (see figure 9). A
master reset activation will reset the interrupt enable flag,
the interrupt pending register and the interrupt active
register. During the power-on reset phase the I/O bus con-
trol signals are set to ’reset mode’ thereby initializing all
on-chip peripherals. All bidirectional ports are set to input
mode. Attention: During any reset phase, the BP20/NTE
input is driven towards V
Releasing the reset results in a short call instruction
(opcode C1h) to the ROM address 008h. This activates
the initialization routine $RESET which in turn has to
initialize all necessary RAM variables, stack pointers and
peripheral configuration registers (see table 7).
Any edge at BP52
any edge at BP53
Timer 1
SSI buffer full / empty or BP40/BP43 interrupt
Timer 2 compare match / overflow
Any edge at BP50,
any edge at BP51
External / internal voltage monitoring
Master Reset
Software interrupt (SWI0)
External hardware interrupt, any edge at BP52
or BP53
Timer 1 interrupt
SSI interrupt or external hardware interrupt at
BP40 or BP43
Timer 2 interrupt
Software interrupt (SW15)
External hardware interrupt, at any edge at
BP50 or BP51
Voltage monitor (VM) interrupt
Interrupt Source
DD
Function
by a strong pull-up transistor.
T6020M
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