st62t62cmae STMicroelectronics, st62t62cmae Datasheet - Page 22

• Manufacturer Part Number: st62t62cmae
• Description: 8-bit Otp/eprom/fastrom Mcus With A/d Converter, Safe Reset, Auto-reload Timer And Eeprom
• Manufacturer: STMicroelectronics

ST62T52CM-Auto ST62T62CM-Auto
RESETS (Cont’d)
3.2.3 Watchdog Reset
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst oth-
er things, resets the watchdog counter.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
3.2.4 LVD Reset
The on-chip Low Voltage Detector, selectable as
user option, features static Reset when supply
voltage is below a reference value. Thanks to this
feature, external reset circuit can be removed
while keeping the application safety. This SAFE
RESET is effective as well in Power-on phase as
in power supply drop with different reference val-
Figure 14. LVD Reset on Power-on and Power-down (Brown-out)
3.2.5 Application Notes
No external resistor is required between V
the Reset pin, thanks to the built-in pull-up device.
22/72
V
V
V
DD
dn
Up
RESET
DD
and
ues, allowing hysteresis effect. Reference value in
case of voltage drop has been set lower than the
reference value for power-on in order to avoid any
parasitic Reset when MCU start's running and
sinking current on the supply.
As long as the supply voltage is below the refer-
ence value, there is a internal and static RESET
command. The MCU can start only when the sup-
ply voltage rises over the reference value. There-
fore, only two operating mode exist for the MCU:
RESET active below the voltage reference, and
running mode over the voltage reference as
shown on the
up, power-down sequence.
Note: When the RESET state is controlled by one
of the internal RESET sources (Low Voltage De-
tector, Watchdog, Power on Reset), the RESET
pin is tied to low logic level.
Direct external connection of the pin RESET to
V
haviour of the internal reset sources (AND.Wired
structure).
DD
must be avoided in order to ensure safe be-
Figure
14., that represents a power-
RESET
time
VR02106A