st62t62b STMicroelectronics, st62t62b Datasheet - Page 44

• Manufacturer Part Number: st62t62b
• Description: 8-bit Otp/eprom Mcus With A/d Converter, Auto-reload Timer And Eeprom
• Manufacturer: STMicroelectronics

44
ST62T52B ST62T62B/E62B
AUTO-RELOAD TIMER (Cont’d)
AR Status Control Register 1(ARSC1)
Address: D7h — Read/Write
Bist 7-5 = PS2-PS0: Prescaler Division Selection
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio is listed in the
following table:
Table 14. . Prescaler Division Ratio Selection
Bit 4 = D4: Reserved . Must be kept reset.
Bit 3-2 = SL1-SL0: Timer Input Edge Control Bits 1-
0. These bits control the edge function of the Timer
input pin for external synchronization. If bit SL0 is
reset, edge detection is disabled; if set edge detec-
tion is enabled. If bit SL1 is reset, the AR Timer input
pin is rising edge sensitive; if set, it is falling edge
sensitive.
Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
the clock sources is explained in the following
15 . Clock Source
Table 15. . Clock Source Selection.
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PS2
PS2
7
0
0
0
0
1
1
1
1
CC1
SL1
X
0
1
0
0
1
1
PS1
PS1
0
0
1
1
0
0
1
1
PS0
CC0
SL0
0
1
1
0
1
0
1
PS0
Selection.:
0
1
0
1
0
1
0
1
D4
Disabled
Rising Edge
Falling Edge
F
F
ARTIMin Input Clock
Reserved
int
int
Divided by 3
SL1
ARPSC Division Ratio
Edge Detection
Clock Source
SL0
128
16
32
64
1
2
4
8
CC1
Table
CC0
0
AR Load Register ARLR. The ARLR load regis-
ter is used to read or write the ARTC counter reg-
ister “on the fly” (while it is counting). The ARLR
register is not affected by system reset.
AR Load Register (ARLR)
Address: DBh — Read/Write
Bit 7-0 = D7-D0: Load Register Data Bits. These
are the load register data bits.
AR Reload/Capture Register. The ARRC re-
load/capture register is used to hold the auto-re-
load value which is automatically loaded into the
counter when overflow occurs.
AR Reload/Capture (ARRC)
Address: D9h — Read/Write
Bit 7-0 = D7-D0: Reload/Capture Data Bits . These
are the Reload/Capture register data bits.
AR Compare Register. The CP compare register
is used to hold the compare value for the compare
function.
AR Compare Register (ARCP)
Address: DAh — Read/Write
Bit 7-0 = D7-D0: Compare Data Bits . These are
the Compare register data bits.
D7
D7
D7
7
7
7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
0
0
0