st62t25cn6 STMicroelectronics, st62t25cn6 Datasheet - Page 42

• Manufacturer Part Number: st62t25cn6
• Description: 8-bit Mcus With A/d Converter, Two Timers, Oscillator Safeguard & Safe Reset
• Manufacturer: STMicroelectronics

ST6215C/ST6225C
I/O PORTS (Cont’d)
8.5 REGISTER DESCRIPTION
DATA REGISTER (DR)
Port x Data Register
DRx with x = A, B or C.
Addresses 0C0h, 0C1h and 0C2h- Read /Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = DR[7:0] Data register bits.
Reading the DR register returns either the DR reg-
ister latch content (pin configured as output) or the
digital value applied to the I/O pin (pin configured
as input).
Caution: In input mode, modifying this register will
modify the I/O port configuration (see
Do not use the Single bit instructions on I/O port
data registers. See
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
DDRx with x = A, B or C.
Addresses: 0C4h, 0C5h and 0C6h - Read /Write
Reset Value: 0000 0000 (00h)
Table 10. I/O Port Register Map and Reset Values
42/105
1
DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0
DR7
Address
of all I/O port registers
7
7
(Hex.)
0CCh
0CDh
0C5h
0C6h
0CEh
0C0h
0C1h
0C2h
0C4h
Reset Value
DR6
DRA
DRB
DRC
DDRA
DDRB
DDRC
ORA
ORB
ORC
DR5
Register
Label
(Section
DR4
DR3
MSB
MSB
MSB
8.2.5).
7
0
DR2
Table
DR1
6
0
8).
DR0
0
0
5
0
Bits 7:0 = DDR[7:0] Data direction register bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
OPTION REGISTER (OR)
Port x Option Register
ORx with x = A, B or C.
Addresses: 0CCh, 0CDh and 0CEh - Read /Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = OR[7:0] Option register bits.
The OR register allows to distinguish in output
mode if the push-pull or open drain configuration is
selected.
Output mode:
0: Open drain output(with P-Buffer deactivated)
1: Push-pull Output
Input mode: See
Each bit is set and cleared by software.
Caution: Modifying this register, will also modify
the I/O port configuration in input mode. (see
ble
OR7
7
8).
4
0
OR6
OR5
3
0
Table
OR4
8.
2
0
OR3
OR2
1
0
OR1
LSB
LSB
LSB
OR0
0
0
0
Ta-