mcf5249pb Freescale Semiconductor, Inc, mcf5249pb Datasheet - Page 10

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mcf5249pb

Manufacturer Part Number
mcf5249pb
Description
Mcf5249 Integrated Coldfire Microprocessor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MCF5249 Functional Overview
The CD-ROM encoder performs following functions in hardware:
1.5.13 Dual UART Module
Two full-duplex UARTs with independent receive and transmit buffers are in this module. Data formats can
be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. Four-byte receive
buffers and two-byte transmit buffers minimize CPU service calls. The Dual UART module also provides
several error-detection and maskable-interrupt capabilities. Modem support includes request-to-send (RTS)
and clear-to-send (CTS) lines.
The system clock provides the clocking function from a programmable prescaler. You can select full duplex,
auto-echo loopback, local loopback, and remote loopback modes. The programmable Dual UARTs can
interrupt the CPU on various normal or error-condition events.
1.5.14 Queued Serial Peripheral Interface QSPI
The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to 16
stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers of up to
17.5 Mbits/second are possible at a CPU clock of 140 MHz. The QSPI supports master mode operation only.
1.5.15 Timer Module
The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer
for use in any of three modes:
The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is derived
from the system clock. In addition to the ÷1 and ÷16 clock derived from the bus clock (CPU clock / 2), the
programmable timer-output pins either generate an active-low pulse or toggle the outputs.
1.5.16 IDE and SmartMedia Interfaces
The MCF5249 system bus allows connection of an IDE hard disk drive and SmartMedia flash card with a
minimum of external hardware. The external hardware consists of bus buffers for address and data and are
intended to reduce the load on the bus and prevent SDRAM and Flash accesses to propagate to the IDE bus.
The control signals for the buffers are generated in the MCF5249.
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1. Input Capture. This mode captures the timer value with an external event.
2. Output Compare. This mode triggers an external signal or interrupts the CPU when the timer
3. Event Counter. This mode counts external events.
Verification of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors
Third-layer error correction is not performed
Sector sync recognition
Scrambling of sectors
Insertion of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors.
Third-layer error encoding needs to be done in software. This can use approximately 5–10 MHz of
performance for single-speed.
reaches a set value
MCF5249 Integrated ColdFire® Microprocessor Product Brief
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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