nt1gt64u8hb0by Nanya Techology, nt1gt64u8hb0by Datasheet - Page 16
nt1gt64u8hb0by
Manufacturer Part Number
nt1gt64u8hb0by
Description
256mb 32m X 64 / 512mb 64m X 64 / 1gb 128m X 64 Unbuffered Ddr2 Sdram Dimm
Manufacturer
Nanya Techology
Datasheet
1.NT1GT64U8HB0BY.pdf
(24 pages)
Note:
Symbol
I
I
I
I
I
I
I
I
NT256T64UH4B0FY / NT512T64U88B0BY / NT1GT64U8HB0BY
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
Operating, Standby, and Refresh Currents
T
I
I
DD3PS
I
I
I
REV 1.2
03/2007
DD3PF
DD4W
DD2Q
DD2P
DD2N
DD3N
DD4R
DD0
DD1
DD5
DD6
DD7
CASE
= 0 ° C ~ 85 °C; V
Operating Current: one bank; active/precharge; t
(MIN);
and control inputs changing once per clock cycle
Operating Current: one bank; active/read/precharge; Burst = 2; t
(MIN);
changing once per clock cycle
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE ≤ V
Idle Standby Current: CS ≥ V
t
Precharge standby current; All banks idle; t
is high; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING.
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ V
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ V
Active Standby Current: one bank; active/precharge; CS ≥ V
V
twice per clock cycle; address and control inputs changing once per clock
cycle
Operating Current: one bank; Burst = 2; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs
changing twice per clock cycle; CL=2.5; t
Operating Current: one bank; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 2.5; t
Auto-Refresh Current: t
Self-Refresh Current: CKE ≤ 0.2V
Operating Current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every
transfer; t
CK
IH
(MIN);
(MIN);
DQ, DM, and DQS inputs changing twice per clock cycle; address
CL=2.5; t
address and control inputs changing once per clock cycle
IL
IL
t
RC
RC
(MAX);
(MAX);
= t
= t
DDQ
Module IDD was calculated from component IDD. It may differ from the actual measurement.
RC
CK
RAS
IL (MAX);
= V
t
t
(min); I
CK
CK
= t
(MAX)
= t
= t
DD
CK
CK
CK
(MIN);
= 1.8V ± 0.1V (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs)
; t
RC
t
OUT
CK
(MIN); Fast PDN Exit MRS(12) = 0mA
(MIN); Slow PDN Exit MRS(12) = 1mA
CK
= t
Parameter/Condition
= t
= t
I
RFC
= 0mA.
OUT
IH
CK
CK
(MIN);
(MIN)
(MIN)
= 0mA; address and control inputs
(MIN)
all banks idle; CKE ≥ V
; DQ, DM, and DQS inputs changing
CK
CK
CK
= t
= t
CK
= t
CK
RC
(MIN)
CK
(MIN);
= t
(IDD); CKE is high; CS
RC
I
OUT
(MIN);
16
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
= 0mA
IH
IH
(MIN)
t
(MIN);
CK
RC
= t
; t
= t
CK
CKE ≥
CK
RC
=
PC2-4200
(-37B)
1040
340
380
160
140
112
172
540
560
600
28
36
28
PC2-5300
(-3C)
1080
360
420
200
160
132
200
640
640
640
28
36
28
PC2-6400
© NANYA TECHNOLOGY CORP.
(-25D)
1080
400
460
204
180
156
240
680
700
700
28
36
28
PC2-6400
(-25C)
1080
400
460
204
180
156
240
680
700
700
28
36
28
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA