nt2gc72c89b0nf Nanya Techology, nt2gc72c89b0nf Datasheet

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nt2gc72c89b0nf

Manufacturer Part Number
nt2gc72c89b0nf
Description
Unbuffered Ddr3 Sdram Dimm With Ecc
Manufacturer
Nanya Techology
Datasheet
NT2GC72C89B0NF / NT4GC72C8PB0NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
Based on DDR3-1066/1333 256Mx8 SDRAM B-Die
Features
•Performance:
DIMM CAS Latency
fck – Clock Freqency
tck – Clock Cycle
fDQ – DQ Burst Freqency
• 240-Pin Dual In-Line Memory Module (UDIMM)
• 256Mx72 and 512Mx72 DDR3 Unbuffered DIMM with ECC based
• Intended for 533MHz/667MHz applications
•V
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
• Nominal and Dynamic On-Die Termination support
• Halogen free product
Description
NT2GC72C89B0NF and NT4GC72C8PB0NF are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Unbuffered Dual In-Line
Memory Module with ECC (UDIMM w/ ECC), organized as one rank of 256Mx72 (2GB) and two ranks of 512Mx72 (4GB) high-speed
memory array. Modules use nine 256Mx8 (2GB) 78-ball BGA packaged devices and eighteen 256Mx8 (4GB) 78-ball BGA packaged
devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these
common design files minimizes electrical variation between suppliers. All NANYA DDR3 SDRAM DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of
1066Mbps/1333Mbps. Prior to any access operation, the device  latency and burst/length/operation type must be programmed into the
DIMM by address inputs A0-A13 and I/O inputs BA0~BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 0.1
02/2010
on 256Mx8 DDR3 SDRAM B-Die devices.
DD
clock edge
= V
Speed Sort
DDQ
= 1.35V+0.0675/-0.1V
PC3-8500
1.875
1066
-BE
533
7
PC3-10600
1333
-CG
667
1.5
9
Mbps
MHz
Unit
ns
1
• Programmable Operation:
• Two different termination values (Rtt_Nom & Rtt_WR)
• 14/11/1 (row/column/rank) Addressing for 2GB
• 14/11/2 (row/column/rank) Addressing for 4GB
• Extended operating temperature rage
• Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
• SDRAMs are in 78-ball BGA Package
• RoHS compliance
- DIMM  Latency: 6,7,8,9
- Burst Type: Sequential or Interleave
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION

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