mma2602wr2 Freescale Semiconductor, Inc, mma2602wr2 Datasheet - Page 16
![no-image](/images/manufacturer_photos/0/2/263/freescale_semiconductor__inc_sml.jpg)
mma2602wr2
Manufacturer Part Number
mma2602wr2
Description
Dsi Inertial Sensor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MMA2602WR2.pdf
(48 pages)
16
3.1.5
register is included in the user register CRC check. Refer to
ble OTP array.
3.1.5.1
Reference
3.1.5.2
Modulated signal proportional to the acceleration response. Reference
output. When the PCM output is cleared, the PCM output pin is actively pulled low. This bit can be factory or user programmed.
3.1.5.3
‘0000’, there is not pre-programmed address, and the address must be assigned via the Initialization DSI command. Reference
Section 4.2.1.1
3.1.6
formation. These registers have no impact on the device performance, but are included in the user register CRC check. Refer to
Section 3.2.2 for details regarding the user register CRC check. These registers can be factory or user programmed.
MMA26xxWR
Table 6. Device Control Register
Device configuration register 2 is a user programmable OTP register which contains device configuration information. This
The LOCK_U bit is a factory or user programmed OTP bit which inhibits writes to the user configuration array when active.
The PCM Bit enables the PCM output pin. When the PCM bit is set, the PCM output pin is active and outputs a Pulse Code
The Device Address bits define the pre-programmed DSI Bus device address. If the Device Address bits are programmed to
The User Data Registers are user programmable OTP register which can be programmed with user or assembly specific in-
RA[3:0]
RA[3:0]
$07
$0C
$0D
$08
$09
$0A
$0B
$0E
$0F
Factory Default
Device Configuration 2 Register (DEVCFG2)
User Data Registers (UDx)
Location
Factory Default
Section 3.2.2
Location
User Configuration Lock Bit (LOCK_U, DEVCFG2[7])
PCM Bit (DEVCFG2[5])
Device Address (ADDR[3:0], DEVCFG2[3:0])
for more details regarding the Initialization DSI command. These bits can be factory or user programmed.
Register
DEVCFG2
Register
UD01
UD02
UD03
UD04
UD05
UD06
UD07
UD08
for details regarding the LOCK_U bit and CRC verification.
WA[3:0]
Bnk3 $0F
Bnk0 $07
Bnk2 $07
Bnk3 $07
WA[3:0]
Bnk2 $0C
Bnk2 $0D
Bnk2 $08
Bnk2 $09
Bnk2 $0A
Bnk2 $0B
Bnk2 $0E
Bnk2 $0F
LOCK_U
UD01[7]
UD02[7]
UD03[7]
UD04[7]
UD05[7]
UD06[7]
UD07[7]
UD08[7]
7
0
7
0
UNUSED
UD01[6]
UD02[6]
UD03[6]
UD04[6]
UD05[6]
UD06[6]
UD07[6]
UD08[6]
6
0
6
0
UD01[5]
UD02[5]
UD03[5]
UD04[5]
UD05[5]
UD06[5]
UD07[5]
UD08[5]
Section 3.2.2
PCM
5
0
5
0
RESERVED
UD01[4]
UD02[4]
UD03[4]
UD04[4]
UD05[4]
UD06[4]
UD07[4]
UD08[4]
4
Section 3.5.3.6
0
4
0
for details regarding the CRC for the user programma-
Bit
Bit
WA[3:0]
WA[3:0]
Bnk1 $0C
Bnk1 $0D
Bnk1 $07
Bnk1 $08
Bnk1 $09
Bnk1 $0A
Bnk1 $0B
Bnk1 $0E
Bnk1 $0F
for more information regarding the PCM
ADDR[3]
UD01[3]
UD02[3]
UD03[3]
UD04[3]
UD05[3]
UD06[3]
UD07[3]
UD08[3]
3
3
0
0
UD01[2]
UD02[2]
UD03[2]
UD04[2]
UD05[2]
UD06[2]
UD07[2]
UD08[2]
ADDR[2]
2
0
2
0
Freescale Semiconductor
UD01[1]
UD02[1]
UD03[1]
UD04[1]
UD05[1]
UD06[1]
UD07[1]
UD08[1]
ADDR[1]
1
0
1
0
UD01[0]
UD02[0]
UD03[0]
UD04[0]
UD05[0]
UD06[0]
UD07[0]
UD08[0]
ADDR[0]
0
0
Sensors
0
0